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ACPL-071L PDF预览

ACPL-071L

更新时间: 2024-09-25 12:36:51
品牌 Logo 应用领域
安华高科 - AVAGO 光电
页数 文件大小 规格书
12页 540K
描述
Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature

ACPL-071L 数据手册

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ACPL-071L and ACPL-074L  
Single-channel and Dual-channel High Speed 15 MBd  
CMOS optocoupler with Glitch-Free Power-Up Feature  
Data Sheet  
Lead (Pb) Free  
RoHS 6 fully  
compliant  
RoHS 6 fully compliant options available;  
-xxxE denotes a lead-free product  
Description  
Features  
The ACPL-071L (single-channel) and ACPL-074L (dual-  
channel) are 15 MBd CMOS optocouplers in SOIC-8 pack-  
age. The optocouplers utilize the latest CMOS IC technol-  
ogy to achieve outstanding performance with very low  
power consumption. Basic building blocks of ACPL-071L  
and ACPL-074L are high speed LEDs and CMOS detector  
ICs. Each detector incorporates an integrated photodiode,  
a high speed transimpedance amplifier, and a voltage  
comparator with an output driver.  
+3.3V and +5 V CMOS compatibility  
30 ns max. pulse width distortion  
40ns max. propagation delay (for 3.3V supply voltage)  
30 ns max. propagation delay skew  
High speed: 15 MBd min  
10 kV/µs minimum common mode rejection  
–40 to 105°C temperature range  
Glitch-Free Power-Up Feature  
Component Image  
Safety and regulatory approvals pending:  
UL recognized  
ACPL-071L  
NC  
1
2
8
VDD  
3750 V rms for 1 min. per UL 1577  
CSA component acceptance Notice #5  
IEC/EN/DIN EN 60747-5-2 approved Option 060  
7
6
ANODE  
NC  
VO  
3
4
Applications  
CATHODE  
NC  
Digital field bus isolation:  
CANBus, RS485, USB  
5
GND  
SHIELD  
ACPL-074L  
Multiplexed data transmission  
Computer peripheral interface  
Microprocessor system interface  
DC/DC converter  
1
ANODE1  
VDD  
Vo1  
8
7
CATHODE1  
CATHODE2  
2
3
Vo2  
6
5
4
ANODE2  
GND  
SHIELD  
TRUTH TABLE  
LED  
OFF  
ON  
V , OUTPUT  
H
O
L
A 0.1uF bypass capacitor must be connected between pins 5 and 8.  
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  

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