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ACMDL-10 PDF预览

ACMDL-10

更新时间： 2024-11-05 08:45:31
品牌 Logo 应用领域
RHOMBUS-IND 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
1页 43K
描述
Logic Buffered Single - Dual - Triple Independent Delay Modules

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中文翻译

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ACMDL-10 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65Is Samacsys：N
系列：ACTJESD-30 代码：R-PDIP-T8
负载电容（CL）：50 pF逻辑集成电路类型：ACTIVE DELAY LINE
功能数量：1抽头/阶步数：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
可编程延迟线：NO认证状态：Not Qualified
座面最大高度：6.35 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
总延迟标称（td）：10 ns宽度：7.62 mm
Base Number Matches：1

ACMDL-10 数据手册

  
• FAST / TTL •  
Electrical Specifications at 25OC  
Logic Buffered Single - Dual - Triple  
Independent Delay Modules  
GENERAL: For Operating Specifications and Test  
FAST Buffered  
Delay  
(ns)  
Single  
Dual  
Triple  
8-Pin P/N  
8-Pin P/N  
8-Pin P/N  
FAMDL-4  
FAMDL-5  
FAMDL-6  
FAMDL-7  
FAMDL-8  
FAMDL-9  
FAM2D-4  
FAM2D-5  
FAM2D-6  
FAM2D-7  
FAM2D-8  
FAM2D-9  
FAM3D-4  
FAM3D-5  
FAM3D-6  
FAM3D-7  
FAM3D-8  
FAM3D-9  
4 ± 1.00  
5 ± 1.00  
Pa rt Num b e r  
Conditions refer to corresponding 5-Tap Series  
FAMDM, ACMDM and LVMDM except Minimum  
Pulse width and Supply current ratings as below.  
Delays specified for the Leading Edge.  
De sc rip tion  
74ACT -- ACMDL  
ACM2D & ACM3D  
XXXXX - XXX X  
6 ± 1.00  
7 ± 1.00  
8 ± 1.00  
74F -- FAMDL  
FAM2D & FAM3D  
Operating Temperature Range  
9 ± 1.00  
FAST/TTL ..................................... 0OC to +70OC  
FAMDL-10 FAM2D-10 FAM3D-10  
FAMDL-12 FAM2D-12 FAM3D-12  
FAMDL-15 FAM2D-15 FAM3D-15  
FAMDL-16 FAM2D-16 FAM3D-16  
FAMDL-20 FAM2D-20 FAM3D-20  
FAMDL-25 FAM2D-25 FAM3D-25  
FAMDL-30 FAM2D-30 FAM3D-30  
10 ± 1.50  
12 ± 1.50  
15 ± 1.50  
16 ± 1.50  
20 ± 2.00  
25 ± 2.00  
30 ± 2.00  
50 ± 2.50  
75 ± 3.75  
100 ± 5.0  
74LVC -- LVMDL  
LVM2D & LVM3D  
74ACT  
74LVC  
.................................. -40OC to +85OC  
.................................. -40OC to +85OC  
Delay Per Line (ns)  
Lead Style:  
Temp. Coefficient of Delay:  
Single.................... 500ppm/OC typical  
Dual/Triple ............ 800ppm/OC typical  
Blank = Auto-Insertable DIP  
G = “Gull Wing” Surface Mount  
J = “J” Bend Surface Mount  
Minimum Input Pulse Width:  
Single..................... 40% of total delay  
Dual/Triple ........... 100% of total delay  
Examples:  
FAMDL-50  
FAMDL-75  
FAMDL-100  
---  
---  
---  
---  
---  
---  
FAMDL-4 = 4ns Single 74F, DIP  
Supply Current, ICC  
:
FAST/TTL FAMDL ........ 25 mA typ., 48 mA max.  
FAM2D ........ 32 mA typ., 65 mA max.  
FAM3D ........ 45 mA typ., 95 mA max.  
ACM2D-25G = 25ns Dual ACT, G-SMD  
LVM3D-30G = 30ns Triple LVC, G-SMD  
74ACT  
ACMDL ........ 14 mA typ., 28 mA max.  
ACM2D ......... 23 mA typ., 52 mA max.  
ACM3D ........ 34 mA typ., 75 mA max.  
• Advanced CMOS •  
Electrical Specifications at 25OC  
74LVC  
LVMDL......... 10 mA typ., 30 mA max.  
LVM2D......... 15 mA typ., 44 mA max.  
LVM3D......... 21 mA typ., 64 mA max.  
74ACT Adv. CMOS  
Delay  
(ns)  
Single  
8-Pin P/N  
Dual  
8-Pin P/N  
Triple  
8-Pin P/N  
Dimensions in Inches (mm)  
Single 8-Pin "DL"  
Schematic  
ACMDL-6  
ACMDL-7  
ACMDL-8  
ACMDL-9  
ACM2D-6  
ACM2D-7  
ACM2D-8  
ACM2D-9  
ACM3D-6  
ACM3D-7  
ACM3D-8  
ACM3D-9  
6 ± 1.00  
7 ± 1.00  
.285  
.505  
Vcc  
OUT  
(12.83)  
MAX.  
(7.24)  
MAX.  
8 ± 1.00  
8
6
5
7
9 ± 1.00  
.020  
(0.51)  
TYP.  
.250  
ACMDL-10 ACM2D-10 ACM3D-10  
ACMDL-12 ACM2D-12 ACM3D-12  
ACMDL-15 ACM2D-15 ACM3D-15  
ACMDL-16 ACM2D-16 ACM3D-16  
ACMDL-20 ACM2D-20 ACM3D-20  
ACMDL-25 ACM2D-25 ACM3D-25  
ACMDL-30 ACM2D-30 ACM3D-30  
10 ± 1.50  
12 ± 1.50  
15 ± 1.50  
16 ± 1.50  
20 ± 2.00  
25 ± 2.00  
30 ± 2.00  
50 ± 2.50  
75 ± 3.75  
100 ± 5.0  
(6.35)  
MAX.  
.010  
(0.25)  
TYP.  
.120  
(3.05)  
MIN.  
.300  
(7.62)  
1
2
3
4
.365  
(9.27)  
MAX.  
GND  
IN  
.020 .050  
.100  
(2.54)  
TYP.  
(0.51)  
TYP.  
(1.27)  
TYP.  
ACMDL-50  
ACMDL-75  
ACMDL-100  
---  
---  
---  
---  
---  
---  
Dual 8-Pin "2D"  
Schematic  
Vcc OUT  
OUT  
.285  
(7.24)  
MAX.  
.505  
(12.83)  
MAX.  
1
2
8
6
5
7
• Low Voltage CMOS •  
.250  
(6.35)  
MAX.  
G-SMD  
G-SMD  
.008 R  
(0.20)  
Electrical Specifications at 25OC  
Low Voltage CMOS Buffered  
Delay  
(ns)  
.010  
(0.25)  
TYP.  
Single  
Dual  
Triple  
.030  
(0.76)  
TYP.  
.430 (10.92)  
.400 (10.16)  
8-Pin P/N  
8-Pin P/N  
8-Pin P/N  
.015  
(0.38)  
TYP.  
1
2
3
4
.020 .050  
.100  
LVMDL-4  
LVMDL-5  
LVMDL-6  
LVMDL-7  
LVMDL-8  
LVMDL-9  
LVM2D-4  
LVM2D-5  
LVM2D-6  
LVM2D-7  
LVM2D-8  
LVM2D-9  
LVM3D-4  
LVM3D-5  
LVM3D-6  
LVM3D-7  
LVM3D-8  
LVM3D-9  
4 ± 1.00  
5 ± 1.00  
(0.51)  
(1.27) (2.54)  
GND  
IN  
IN  
TYP. TYP. TYP.  
1
2
6 ± 1.00  
7 ± 1.00  
.285  
(7.24)  
MAX.  
.505  
(12.83)  
MAX.  
Triple 8-Pin "3D"  
Schematic  
8 ± 1.00  
9 ± 1.00  
Vcc OUT OUT OUT  
3
1
2
LVMDL-10 LVM2D-10 LVM3D-10  
LVMDL-12 LVM2D-12 LVM3D-12  
LVMDL-15 LVM2D-15 LVM3D-15  
LVMDL-16 LVM2D-16 LVM3D-16  
LVMDL-20 LVM2D-20 LVM3D-20  
LVMDL-25 LVM2D-25 LVM3D-25  
LVMDL-30 LVM2D-30 LVM3D-30  
10 ± 1.50  
12 ± 1.50  
15 ± 1.50  
16 ± 1.50  
20 ± 2.00  
25 ± 2.00  
30 ± 2.00  
50 ± 2.50  
75 ± 3.75  
100 ± 5.0  
.265  
(6.73)  
MAX.  
J-SMD  
J-SMD  
8
7
6
5
.020 R  
(0.51)  
.285 (7.24)  
.260 (6.60)  
.030  
(0.76)  
TYP.  
.020 .050  
.100  
.330 (8.38)  
MAX.  
(0.51)  
TYP.  
(2.54)  
(1.27)  
TYP. TYP.  
1
2
3
IN  
4
LVMDL-50  
LVMDL-75  
LVMDL-100  
---  
---  
---  
---  
---  
---  
GND  
IN  
IN  
2
1
3
www.rhombus-ind.com  
sales@rhombus-ind.com  
20  
TEL: (714) 898-0960  
FAX: (714) 896-0971  
LOGBUF3D 2001-01  
1

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