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ACE1501EMT PDF预览

ACE1501EMT

更新时间: 2024-01-12 15:40:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 外围集成电路光电二极管微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数 文件大小 规格书
33页 1185K
描述
ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications

ACE1501EMT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP8,.3
针数:8Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.79
具有ADC:NO地址总线宽度:
位大小:8CPU系列:ACE1502
最大时钟频率:25 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:R-PDIP-T8长度:9.817 mm
I/O 线路数量:6端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP8,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8/3.6 V
认证状态:Not QualifiedRAM(字节):64
ROM(单词):1088ROM可编程性:EEPROM
座面最大高度:5.08 mm速度:25 MHz
子类别:Microcontrollers最大压摆率:1 mA
最大供电电压:3.6 V最小供电电压:1.8 V
标称供电电压:2.2 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

ACE1501EMT 数据手册

 浏览型号ACE1501EMT的Datasheet PDF文件第25页浏览型号ACE1501EMT的Datasheet PDF文件第26页浏览型号ACE1501EMT的Datasheet PDF文件第27页浏览型号ACE1501EMT的Datasheet PDF文件第29页浏览型号ACE1501EMT的Datasheet PDF文件第30页浏览型号ACE1501EMT的Datasheet PDF文件第31页 
Figure 36. Recommended HALT Flow  
Normal Mode  
LD HALT, #01H  
Multi-Input  
HALT Mode  
Wakeup  
LD PMC, #00H  
Resume Normal  
Mode  
16. IDLE Mode  
In addition to the HALT mode power saving feature, the device  
also supports an IDLE mode operation. The device is placed  
into IDLE mode by setting the IDLE enable bit (EIDLE) of the  
HALT register through software using only the LD M, #instruc-  
tion. EIDLE is a write only bit and is automatically cleared upon  
exiting IDLE. The IDLE mode operation is similar to HALT  
except the internal oscillator, the Watchdog, and the Timer 0  
remain active while the other on-chip systems including the LBD  
and the BOR circuits are shut down.  
The device automatically wakes from IDLE mode by the Timer 0  
overow every 8192 cycles (see Section 5). Before entering  
IDLE mode, software must clear the WKEN register to disable  
the MIW block. Once a wake from IDLE mode is triggered, the  
core will begin normal operation by the next clock cycle. Imme-  
diately after exiting IDLE mode, software must clear the Power  
Mode Clear (PMC) register by using only the LD M, #instruc-  
tion. (See Figure 37.)  
Figure 37. Recommended IDLE Flow  
Normal Mode  
LD  
HALT, #02H  
Timer0  
Underflow  
IDLE Mode  
Multi-Input  
Wakeup  
LD PMC, #00H  
Resume Normal  
Mode  
28  
www.fairchildsemi.com  
ACE1501 Product Family Rev. 1.1  

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