ACE1501EMT

更新时间： 2024-01-16 15:32:08

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		外围集成电路光电二极管微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
33页	1185K
描述
ACE1501 Product Family Arithmetic Controller Engine (ACEx⑩) for Low Power Applications

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中文翻译

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技术参数
数据手册

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ACE1501EMT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	DIP	包装说明：	DIP, DIP8,.3
针数：	8	Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01	风险等级：	5.79
具有ADC：	NO	地址总线宽度：
位大小：	8	CPU系列：	ACE1502
最大时钟频率：	25 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：
JESD-30 代码：	R-PDIP-T8	长度：	9.817 mm
I/O 线路数量：	6	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-40 °C
PWM 通道：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP8,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.8/3.6 V
认证状态：	Not Qualified	RAM（字节）：	64
ROM（单词）：	1088	ROM可编程性：	EEPROM
座面最大高度：	5.08 mm	速度：	25 MHz
子类别：	Microcontrollers	最大压摆率：	1 mA
最大供电电压：	3.6 V	最小供电电压：	1.8 V
标称供电电压：	2.2 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER
Base Number Matches：	1

ACE1501EMT 数据手册

12. RESET block

When a RESET sequence is initiated, all I/O registers will be

reset setting all I/Os to high-impedence inputs. The system

clock is restarted after the required clock start-up delay. A reset

is generated by any one of the following four conditions:

•

Power-on Reset (as described in Section 13)

Brown-out Reset (as described in Section 11.1)

Watchdog Reset (as described in Section 6)

External Reset (as described in Section 13)

18. Available only on the 14-pin package option

13. Power-On Reset

The Power-On Reset (POR) circuit is guaranteed to work if the

rate of rise of Vcc is no slower than 10ms/1volt. The POR circuit

was designed to respond to fast low to high transitions between

0V and Vcc. The circuit will not work if Vcc does not drop to 0V

before the next power-up sequence. In applications where 1)

the Vcc rise is slower than 10ms/1 volt or 2) Vcc does not drop

to 0V before the next power-up sequence the external reset

option should be used.

The external reset provides a way to properly reset the ACEx

microcontroller if POR cannot be used in the application. The

external reset pin contains an internal pull-up resistor. There-

fore, to reset the device the reset pin should be held low for at

least 2ms so that the internal clock has enough time to stabilize.

14. CLOCK

The ACEx microcontroller has an on-board oscillator trimmed to

a frequency of 2MHz who is divided down by two yielding a

1MHz frequency. (See AC Electrical Characteristics) Upon

power-up, the on-chip oscillator runs continuously unless enter-

ing HALT mode or using an external clock source.

Figure 34. Crystal

CKI

CKO

If required, an external oscillator circuit may be used depending

on the states of the CMODE bits of the initialization register.

(See Table 16) When the device is driven using an external

clock, the clock input to the device (G1/CKI) can range between

DC to 4MHz. For external crystal conﬁguration, the output clock

(CKO) is on the G0 pin. (See Figure 34.) If the device is conﬁg-

ured for an external square clock, it will not be divided.

Table 16. CMODEx Bit Deﬁnition

CMODE [1] CMODE [0]

Clock Type

Internal 1 MHz clock

External square clock

External crystal/resonator

Reserved

15. HALT Mode

The HALT mode is a power saving feature that almost com-

pletely shuts down the device for current conservation. The

device is placed into HALT mode by setting the HALT enable bit

(EHALT) of the HALT register through software using only the

“LD M, #” instruction. EHALT is a write only bit and is automati-

cally cleared upon exiting HALT. When entering HALT, the inter-

nal oscillator and all the on-chip systems including the LBD and

the BOR circuits are shut down.

The device can exit HALT mode only by the MIW circuit. There-

fore, prior to entering HALT mode, software must conﬁgure the

MIW circuit accordingly. (See Section 8) After a wakeup from

HALT, a 1ms start-up delay is initiated to allow the internal oscil-

lator to stabilize before normal execution resumes. Immediately

after exiting HALT, software must clear the Power Mode Clear

(PMC) register by only using the “LD M, #” instruction. (See Fig-

ure 36)

Figure 35. HALT Register Deﬁnition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Undeﬁned

undeﬁned

EIDLE

EHALT

www.fairchildsemi.com

ACE1501 Product Family Rev. 1.1

1...24 25 262728 29 30...33

中文翻译

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与ACE1501EMT相关器件

型号	品牌	获取价格	描述	数据表
ACE1501EMT8	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501EMT8X	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501EMTX	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501EMX	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501EN	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501EN14	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501V	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501VM	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501VM8	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller
ACE1501VM8X	FAIRCHILD	获取价格	ACE1501 Product Family Arithmetic Controller

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