Datasheet > A80960MC-25

A80960MC-25

更新时间： 2024-11-08 23:26:51

品牌	Logo	应用领域
其他 - ETC		外围集成电路时钟
页数	文件大小	规格书
39页	393K
描述
MICROPROCESSOR\|32-BIT\|CMOS\|PGA\|132PIN\|CERAMIC

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数据手册

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A80960MC-25 数据手册

80960MC

EMBEDDED 32-BIT MICROPROCESSOR

WITH INTEGRATED FLOATING-POINT UNIT

AND MEMORY MANAGEMENT UNIT

Commercial

■ High-Performance Embedded Architecture

■ On-Chip Memory Management Unit

— 25 MIPS Burst Execution at 25 MHz

— 9.4 MIPS* Sustained Execution at

25 MHz

— 4 Gbyte Virtual Address Space per

Task

— 4 Kbyte Pages with Supervisor/User

Protection

■ On-Chip Floating Point Unit

■ Built-in Interrupt Controller

— 32 Priority Levels

— Supports IEEE 754 Floating Point

Standard

— Full Transcendental Support

— Four 80-Bit Registers

— 13.6 Million Whetstones/s

(Single Precision) at 25 MHz

— 248 Vectors

— Supports M8259A

— 3.4 µs Latency @ 25 MHz

■ Easy to Use, High Bandwidth 32-Bit Bus

— 66.7 Mbytes/s Burst

■ 512-Byte On-Chip Instruction Cache

— Direct Mapped

— Parallel Load/Decode for Uncached

Instructions

— Up to 16 Bytes Transferred per Burst

■ Multitasking and Multiprocessor Support

— Automatic Task dispatching

— Prioritized Task Queues

■ Multiple Register Sets

— Sixteen Global 32-Bit Registers

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored

On-Chip (Sixteen 32-Bit Registers per

Set)

■ Advanced Package Technology

— 132-Lead Ceramic Pin Grid Array

— Register Scoreboarding

FOUR

80-BIT FP

REGISTERS

64- BY 32-BIT

LOCAL

CACHE

SIXTEEN

32-BIT GLOBAL

REGISTERS

32-BIT

INSTRUCTION

MMU

EXECUTION

UNIT

80-BIT

FPU

32-BIT

BUS CONTROL

LOGIC

MICRO-

INSTRUCTION

SEQUENCER

512-BYTE

INSTRUCTION

CACHE

MICRO-

INSTRUCTION

ROM

32-BIT

BURST

BUS

INSTRUCTION

FETCH UNIT

INSTRUCTION

DECODER

Figure 1. The 80960MC Processor’s Highly Parallel Architecture

September, 1997

Order Number: 273123-001

12 3 4 5 6 7...39

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