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A6810KLW-T PDF预览

A6810KLW-T

更新时间: 2024-11-18 19:54:43
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动光电二极管接口集成电路
页数 文件大小 规格书
8页 170K
描述
Vacuum Fluorescent Driver, 10-Segment, CMOS, PDSO20, LEAD FREE, MS-013AC, SOIC-20

A6810KLW-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:CAN ALSO OPERATE WITH 5V LOGIC SUPPLY
数据输入模式:SERIAL接口集成电路类型:VACUUM FLUORESCENT DISPLAY DRIVER
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm湿度敏感等级:3
复用显示功能:NO功能数量:1
区段数:10端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3/5,60 V认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Display Drivers
最大压摆率:3 mA标称供电电压:3.3 V
电源电压1-Nom:60 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.5 mm
最小 fmax:10 MHzBase Number Matches:1

A6810KLW-T 数据手册

 浏览型号A6810KLW-T的Datasheet PDF文件第2页浏览型号A6810KLW-T的Datasheet PDF文件第3页浏览型号A6810KLW-T的Datasheet PDF文件第4页浏览型号A6810KLW-T的Datasheet PDF文件第5页浏览型号A6810KLW-T的Datasheet PDF文件第6页浏览型号A6810KLW-T的Datasheet PDF文件第7页 
6810  
DABiC-IV, 10-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVER  
The A6810– devices combine 10-bit CMOS shift registers, accom-  
panying data latches and control circuitry with bipolar sourcing outputs  
and pnp active pull downs. Designed primarily to drive vacuum-uo-  
rescent displays, the 60 V and -40 mA output ratings also allow these  
devices to be used in many other peripheral power driver applications.  
The A6810– feature an increased data input rate (compared with the  
older UCN/UCQ5810-F) and a controlled output slew rate.  
A6810xA  
18 OUT  
17 OUT  
1
2
3
4
OUT  
OUT  
OUT  
9
8
7
6
10  
The CMOS shift register and latches allow direct interfacing with  
microprocessor-based systems. With a 3.3 V or 5 V logic supply, serial-  
data input rates of at least 10 MHz .  
SERIAL  
DATA OUT  
16  
15  
14  
LATCHES  
REGISTER  
LOAD  
SUPPLY  
CLK  
V
BB  
CLOCK  
SERIAL  
DATA IN  
A CMOS serial data output permits cascade connections in appli-  
cations requiring additional drive lines. Similar devices are available as  
the A6812– (20 bits) and A6818– (32 bits).  
GROUND  
5
6
REGISTER  
LATCHES  
LOGIC  
SUPPLY  
V
BLNK 13 BLANKING  
DD  
12 OUT  
7
8
ST  
STROBE  
1
The A6810– output source drivers are npn Darlingtons, capable of  
sourcing up to 40 mA. The controlled output slew rate reduces electro-  
magnetic noise, which is an important consideration in systems that in-  
clude telecommunications and/or microprocessors and to meet govern-  
ment emissions regulations. For inter-digit blanking, all output drivers  
can be disabled and all sink drivers turned on with a BLANKING input  
high. The pnp active pull-downs will sink at least  
11 OUT  
OUT  
5
2
9
10 OUT  
OUT  
4
3
Dwg. PP-029  
2.5 mA.  
The A6810– are available in three temperature ranges for optimum  
performance in commercial (sufx S-), industrial (sufx E-), or au-  
tomtoive (sufx K–) applications. They are provided in two package  
styles for through-hole DIP (sufx -A) or minimum-area surface-mount  
SOIC (sufx -LW). Copper lead frames, low logic-power dissipation,  
and low output-saturation voltages allow all devices to source 25 mA  
from all outputs continuously over the maximum operating temperature  
range.  
ABSOLUTE MAXIMUM RATINGS  
at TA = 25°C  
Logic Supply Voltage, VDD .................. 7.0 V  
Driver Supply Voltage, VBB ................... 60 V  
Continuous Output Current Range,  
IOUT ........................ -40 mA to +15 mA  
Input Voltage Range,  
The lead (Pb) free versions are provided with 100% matte tin  
leadframe plating.  
VIN ....................... -0.3 V to VDD + 0.3 V  
Package Power Dissipation,  
PD ....................................... See Graph  
Operating Temperature Range, TA  
(Sufx ‘E–’) ................... -40°C to +85°C  
(Sufx ‘K–’) ................. -40°C to +125°C  
(Sufx ‘S–’) ................... -20°C to +85°C  
Storage Temperature Range,  
FEATURES  
Controlled Output Slew Rate  
High-Speed Data Storage  
60 V Minimum Output Breakdown  
High Data Input Rate  
TS ............................... -55°C to +125°C  
PNP Active Pull-Downs  
Caution: These CMOS devices have input  
static protection (Class 2) but are still sus-  
ceptible to damage if exposed to extremely  
high static electrical charges.  
Low Output-Saturation Voltages  
Low-Power CMOS Logic and Latches  
Improved Replacements for TL4810–, UCN5810–, and UCQ5810–  

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