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A625308A-70SI PDF预览

A625308A-70SI

更新时间: 2024-02-07 21:02:06
品牌 Logo 应用领域
联笙电子 - AMICC 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
14页 143K
描述
32K X 8 BIT CMOS SRAM

A625308A-70SI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:DIP, DIP28,.6Reach Compliance Code:unknown
风险等级:5.84最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDIP-T28
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.000003 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.035 mA标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

A625308A-70SI 数据手册

 浏览型号A625308A-70SI的Datasheet PDF文件第6页浏览型号A625308A-70SI的Datasheet PDF文件第7页浏览型号A625308A-70SI的Datasheet PDF文件第8页浏览型号A625308A-70SI的Datasheet PDF文件第10页浏览型号A625308A-70SI的Datasheet PDF文件第11页浏览型号A625308A-70SI的Datasheet PDF文件第12页 
A625308A Series  
Timing Waveforms (continued)  
Write Cycle 2 (6)  
(Chip Enable Controlled)  
tWC  
Address  
3
tAW  
tWR  
5
tCW  
CE  
(4)  
1
tAS  
2
tWP  
WE  
tDW  
tDH  
DIN  
7
tWHZ  
DOUT  
Notes: 1. tAS is measured from the address valid to the beginning of Write.  
2. A Write occurs during the overlap (tWP) of a low CE and a low WE .  
3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle.  
4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs  
remain in a high impedance state.  
5. tCW is measured from the later of CE going low to the end of Write.  
6. OE level is high or low.  
7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.  
PRELIMINARY  
(July, 2002, Version 0.2)  
8
AMIC Technology, Inc.  

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