v 3 . 1
54SX Family FPGAs
L e a d i n g E d g e P e r f o r m a n c e
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Set-Up
F e a t u r e s
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• 0.25 ns Clock Skew
• 100% Resource Utilization with 100% Pin Locking
• 3.3V Operation with 5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
S p e c i f i c a t i o n s
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1080 Flip-Flops
• Unique In-System Diagnostic and Debug capability with
Silicon Explorer II
• 0.35µ CMOS
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
S X P r o d u c t P r o f i l e
A54SX08
A54SX16
A54SX16P
A54SX32
Capacity
Typical Gates
System Gates
8,000
12,000
16,000
24,000
16,000
24,000
32,000
48,000
Logic Modules
Combinatorial Cells
768
512
1,452
924
1,452
924
2,880
1800
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
256
130
528
175
528
175
1,080
249
3
3
3
3
JTAG
Yes
Yes
Yes
Yes
PCI
—
—
Yes
—
Clock-to-Out
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
84
208
100
—
208
100
176
—
—
208
100
—
208
—
144, 176
—
144, 176
—
144, 176
313, 329
—
144
—
—
J u n e 2 0 0 3
1
© 2003 Actel Corporation