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A49LF004TL-33 PDF预览

A49LF004TL-33

更新时间: 2024-02-12 01:01:24
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路
页数 文件大小 规格书
32页 585K
描述
Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32

A49LF004TL-33 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:PLASTIC, LEAD FREE, LCC-32Reach Compliance Code:unknown
风险等级:5.62最长访问时间:120 ns
启动块:TOP命令用户界面:YES
数据轮询:YESJESD-30 代码:R-PQCC-J32
长度:13.97 mm内存密度:4194304 bit
内存集成电路类型:FLASH内存宽度:8
功能数量:1部门数/规模:8
端子数量:32字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified就绪/忙碌:YES
座面最大高度:3.4 mm部门规模:64K
最大待机电流:0.0001 A子类别:Flash Memories
最大压摆率:0.024 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
切换位:YES类型:NOR TYPE
宽度:11.43 mmBase Number Matches:1

A49LF004TL-33 数据手册

 浏览型号A49LF004TL-33的Datasheet PDF文件第8页浏览型号A49LF004TL-33的Datasheet PDF文件第9页浏览型号A49LF004TL-33的Datasheet PDF文件第10页浏览型号A49LF004TL-33的Datasheet PDF文件第12页浏览型号A49LF004TL-33的Datasheet PDF文件第13页浏览型号A49LF004TL-33的Datasheet PDF文件第14页 
A49LF004  
Table 6: Lock Register Bit Definition  
Reserved  
Bit 7:3  
Read-Lock Lock-Down  
Write-Lock  
Bit 0  
Data  
Function  
Bit 2  
Bit 1  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
00000  
00000  
00000  
00000  
00000  
00000  
00000  
00000  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full Access.  
Write locked. Default state at power-up.  
Locked open (full access locked down).  
Write-locked down.  
Read locked.  
Read and Write locked.  
Read-locked down  
Read- and Write-locked down  
Data  
Function  
7:3  
Reserved  
Read-Lock  
2
1
0
1 = Prevents read operations in the block where set  
0 = Normal operation for reads in the block where clear. This is the default state.  
Lock-Down  
1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set  
but not clear. The block will remain lock-down until reset (with RST# or INIT# being Low), or until the device  
is power-on reset.  
0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state.  
Write-Lock  
1 = Prevents program or erase operations in the block where set. This is the default state.  
0 = Normal operation for programming and erase in the block where clear.  
Byte-Program Operation  
ADDRESS/ADDRESS MULTIPLEXED (A/A  
MUX) MODE  
The A49LF004 device is programmed on a byte-by-byte  
basis. Before programming, one must ensure that the block,  
in which the byte which is being programmed exists, is fully  
erased. The Byte-Program operation is initiated by executing  
a four-byte command load sequence for Software Data  
Protection with address and data in the last byte sequence.  
During the Byte-Program operation, the row address (A10-A0)  
is latched on the falling edge of R/C# and the column  
Address (A21-A11) is latched on the rising edge of R/C#. The  
data bus is latched in the rising edge of WE#. See Figure 11  
for Program operation timing diagram, Figure 14 for timing  
waveforms, and Figure 19 for its flowchart. During the  
Program operation, the only valid reads are Data# Polling  
and Toggle Bit. During the internal Program operation, the  
host is free to perform additional tasks. Any commands  
written during the internal Program operation will be ignored.  
Device Operation  
Commands are used to initiate the memory operation  
functions of the device. The data portion of the software  
command sequence is latched on the rising edge of WE#.  
During the software command sequence the row address is  
latched on the falling edge of R/C# and the column address  
is latched on the rising edge of R/C#. Refer to Table 7 and  
Table 8 for operation modes and the command sequence.  
Read  
The Read operation of the A49LF004 device is controlled by  
OE#. OE# is the output control and is used to gate data from  
the output pins. Refer to the Read cycle timing diagram,  
Figure 10 for further details.  
Reset  
A VIL on RST# pin initiates a device reset.  
(December, 2005, Version 1.0)  
10  
AMIC Technology, Corp.  

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