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A49LF004TL-33 PDF预览

A49LF004TL-33

更新时间： 2024-02-18 18:22:30
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路
页数 文件大小 规格书
32页 585K
描述
Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32

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A49LF004TL-33 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：PLASTIC, LEAD FREE, LCC-32Reach Compliance Code：unknown
风险等级：5.62最长访问时间：120 ns
启动块：TOP命令用户界面：YES
数据轮询：YESJESD-30 代码：R-PQCC-J32
长度：13.97 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：8
端子数量：32字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：3.4 mm部门规模：64K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.024 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
切换位：YES类型：NOR TYPE
宽度：11.43 mmBase Number Matches：1

A49LF004TL-33 数据手册

 浏览型号A49LF004TL-33的Datasheet PDF文件第7页浏览型号A49LF004TL-33的Datasheet PDF文件第8页浏览型号A49LF004TL-33的Datasheet PDF文件第9页浏览型号A49LF004TL-33的Datasheet PDF文件第11页浏览型号A49LF004TL-33的Datasheet PDF文件第12页浏览型号A49LF004TL-33的Datasheet PDF文件第13页 
A49LF004  
Table 4: FWH Register Memory Map  
Memory  
Mnemonic  
Register Name  
Default  
Type  
Address  
FFBF0002h  
FFBE0002h  
FFBD0002h  
FFBC0002h  
FFBB0002h  
FFBA0002h  
FFB90002h  
FFB80002h  
FFBC0100h  
FFBC0000h  
FFBC0001h  
FFBC0003h  
T_BLOCK_LK  
T_MINUS01_LK  
T_MINUS02_LK  
T_MINUS03_LK  
T_MINUS04_LK  
T_MINUS05_LK  
T_MINUS06_LK  
T_MINUS07_LK  
FGPI_REG  
Top Block Lock Register (Block 7)  
Top Block [-1] Lock Register (Block 6)  
Top Block [-2] Lock Register (Block 5)  
Top Block [-3] Lock Register (Block 4)  
Top Block [-4] Lock Register (Block 3)  
Top Block [-5] Lock Register (Block 2)  
Top Block [-6] Lock Register (Block 1)  
Top Block [-7] Lock Register (Block 0)  
FWH General Purpose Input Register  
Manufacturer ID Register  
01h  
01h  
01h  
01h  
01h  
01h  
01h  
01h  
N/A  
37h  
95h  
7Fh  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
MANUF_REG  
DEV_REG  
R
Device ID Register  
R
CONT_REG  
Continuation ID Register  
R
General Purpose Inputs Register  
Write-Lock.  
The GPI_REG (General Purpose Inputs Register) passes the  
state of FGPI[4:0] pins at power-up on the A49LF004. It is  
recommended that the FGPI[4:0] pins are in the desired state  
before FWH4 is brought low for the beginning of the bus  
cycle, and remain in that state until the end of the cycle.  
There is no default value since this is a pass-through register.  
The GPI register for the boot device appears at FFBC0100H  
in the 4 GByte system memory map, and will appear  
elsewhere if the device is not the boot device. Register is not  
available for read when the device is in Erase/Program  
operation. See Table 5 for the GPI_REG bits and function.  
The Write-Lock Bit determines whether the contents of the  
Block can be modified (using the Program or Erase  
Command). When the Write-Lock Bit is set to ‘1’, the block is  
write protected; any operations that attempt to change the  
data in the block will fail and the Status Register will report  
the error. When the Write-Lock Bit is reset to ‘0’, the block is  
not write protected through the Locking Register and may be  
modified unless write protected through some other means. If  
Top Block Lock, TBL#, is Low, VIL, then the Top Block (Block  
7) is write protected and cannot be modified.  
Similarly, if Write Protect, WP#, is Low, VIL, then the Main  
Blocks (Blocks 0 to 6) are write protected and cannot be  
modified. After power-up or reset the Write-Lock Bit is always  
set to ‘1’ (write protected).  
Table 5: General Purpose Inputs Register  
Bit  
Pin Number  
Bit  
Function  
Read-Lock.  
Name  
32-PLCC 32-TSOP  
The Read-Lock bit determines whether the contents of the  
Block can be read (from Read mode). When the Read-Lock  
Bit is set to ‘1’, the block is read protected; any operation that  
attempts to read the contents of the block will read 00h  
instead. When the Read-Lock Bit is reset to ‘0’, read  
operations in the Block return the data programmed into the  
block as expected. After power-up or reset the Read-Lock Bit  
is always reset to ‘0’ (not read protected).  
7:5  
4
-
Reserved  
-
30  
3
-
FGPI[4]  
FGPI[3]  
FGPI[2]  
FGPI[1]  
FGPI[0]  
GPI_REG Bit 4  
GPI_REG Bit 3  
GPI_REG Bit 2  
GPI_REG Bit 1  
GPI_REG Bit 0  
6
3
11  
12  
13  
14  
2
4
1
5
0
6
Lock-Down. The Lock-Down Bit provides a mechanism for  
protecting software data from simple hacking and malicious  
attack. When the Lock-Down Bit is set to ‘1’, further  
modification to the Write-Lock, Read-Lock and Lock-Down  
Bits cannot be performed. A reset or power-up is required  
before changes to these bits can be made. When the Lock-  
Down Bit is reset to ‘0’, the Write-Lock, Read-Lock and Lock-  
Down Bits can be changed.  
Block Locking Registers  
A49LF004 provides software controlled lock protection  
through a set of Block Locking registers. The Block Locking  
Registers are read/write registers and it is accessible through  
standard addressable memory locations specified in Table 6.  
Unused register locations will read as 00H.  
(December, 2005, Version 1.0)  
9
AMIC Technology, Corp.  
1...78910111213...32

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