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A49LF004TL-33 PDF预览

A49LF004TL-33

更新时间： 2024-02-26 19:34:17
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路
页数 文件大小 规格书
32页 585K
描述
Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32

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A49LF004TL-33 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：PLASTIC, LEAD FREE, LCC-32Reach Compliance Code：unknown
风险等级：5.62最长访问时间：120 ns
启动块：TOP命令用户界面：YES
数据轮询：YESJESD-30 代码：R-PQCC-J32
长度：13.97 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：8
端子数量：32字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：3.4 mm部门规模：64K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.024 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
切换位：YES类型：NOR TYPE
宽度：11.43 mmBase Number Matches：1

A49LF004TL-33 数据手册

 浏览型号A49LF004TL-33的Datasheet PDF文件第4页浏览型号A49LF004TL-33的Datasheet PDF文件第5页浏览型号A49LF004TL-33的Datasheet PDF文件第6页浏览型号A49LF004TL-33的Datasheet PDF文件第8页浏览型号A49LF004TL-33的Datasheet PDF文件第9页浏览型号A49LF004TL-33的Datasheet PDF文件第10页 
A49LF004  
Table 2: FWH Read Cycle  
Clock  
Field  
MEMORY  
I/O  
FWH[3:0]  
Descriptions  
Cycle  
FWH4 must be active (low) for the part to respond. Only the last  
start field (before FWH4 transitioning high) should be recognized.  
The START field contents indicate an FWH read cycle.  
1
2
START  
IDSEL  
1101  
IN  
IN  
Indicates which FWH device should respond. If the IDSEL (ID  
select) field matches the value ID[3:0], then that particular device  
will respond to subsequent commands.  
0000 to 1111  
These seven clock cycles make up the 28-bit memory address.  
YYYY is one nibble of the entire address. Addresses are  
transferred most-significant nibble first.  
3-9  
10  
11  
IMADDR  
IMSIZE  
TAR0  
YYYY  
0000 (1 byte)  
1111  
IN  
IN  
A field of this size indicates how many bytes will be transferred  
during multibyte operations.  
In this clock cycle, the master (Intel ICH) has driven the bus to all  
1s and then floats the bus, prior to the next clock cycle. This is the  
first part of the bus “turnaround cycle.”  
IN  
then float  
Float  
The FWH takes control of the bus during this cycle. During the  
next clock cycle, it will be driven “sync data.”  
12  
13  
TAR1  
1111 (float)  
then OUT  
During this clock cycle, the FWH will generate a “ready-sync”  
(RSYNC) indicating that the least-significant nibble of the least-  
significant byte will be available during the next clock cycle.  
RSYNC  
0000 (READY)  
OUT  
14  
15  
DATA  
DATA  
YYYY  
YYYY  
OUT  
OUT  
YYYY is the least-significant nibble of the data byte.  
YYYY is the most-significant nibble of the data byte.  
In this clock cycle, the A49LF004 has driven the bus to all 1s and  
then floats the bus prior to the next clock cycle. This is the first part  
of the bus “turnaround cycle.”  
OUT  
16  
17  
TAR0  
TAR1  
1111  
then float  
Float  
The master (Intel ICH) resumes control of the bus during this  
cycle.  
1111 (float)  
then IN  
FWH Single-Byte Read Waveforms  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
CLK  
FWH4  
START  
IDSEL  
IMADDR  
IMSIZE  
TAR0  
TAR1  
RSYNC  
DATA  
TAR0  
TAR1  
FWH[3:0]  
(December, 2005, Version 1.0)  
6
AMIC Technology, Corp.  
1...45678910...32

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A49LF004TX-33C AMICC 4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory

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A49LF004TX-33F AMICC Flash, 512KX8, 120ns, PDSO32, 8 X 14 MM, LEAD FREE, TSOP1-32

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