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A49LF004TL-33 PDF预览

A49LF004TL-33

更新时间： 2024-02-22 06:45:00
品牌 Logo 应用领域
联笙电子 - AMICC 内存集成电路
页数 文件大小 规格书
32页 585K
描述
Flash, 512KX8, 120ns, PQCC32, PLASTIC, LCC-32

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A49LF004TL-33 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：PLASTIC, LEAD FREE, LCC-32Reach Compliance Code：unknown
风险等级：5.62最长访问时间：120 ns
启动块：TOP命令用户界面：YES
数据轮询：YESJESD-30 代码：R-PQCC-J32
长度：13.97 mm内存密度：4194304 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：8
端子数量：32字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：
组织：512KX8封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC32,.5X.6
封装形状：RECTANGULAR封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified就绪/忙碌：YES
座面最大高度：3.4 mm部门规模：64K
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.024 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
切换位：YES类型：NOR TYPE
宽度：11.43 mmBase Number Matches：1

A49LF004TL-33 数据手册

 浏览型号A49LF004TL-33的Datasheet PDF文件第2页浏览型号A49LF004TL-33的Datasheet PDF文件第3页浏览型号A49LF004TL-33的Datasheet PDF文件第4页浏览型号A49LF004TL-33的Datasheet PDF文件第6页浏览型号A49LF004TL-33的Datasheet PDF文件第7页浏览型号A49LF004TL-33的Datasheet PDF文件第8页 
A49LF004  
Table 1: Pin Description  
Interface  
A/A  
Mux  
Symbol  
Pin Name  
Type  
Descriptions  
FWH  
Inputs for addresses during Read and Write operations in A/A Mux  
mode. Row and column addresses are latched by R/C# pin.  
A10-A0  
Address  
Data  
IN  
X
To output data during Read cycle and receive input data during  
Write cycle in A/A Mux mode. The outputs are in tri-state when  
OE# is high.  
I/O7-I/O0  
I/O  
X
OE#  
WE#  
Output Enable  
Write Enable  
IN  
IN  
X
X
To control the data output buffers.  
To control the Write operations.  
To determine which interface is operational. When held high, A/A  
Mux mode is enabled and when held low, FWH mode is enabled.  
This pin must be setup at power-up or before return from reset and  
not change during device operation. This pin is internally pulled  
down with a resistor between 20-100 KΩ.  
Interface  
Configuration Pin  
IC  
IN  
IN  
X
X
X
This is the second reset pin for in-system use. INIT# and RST#  
pins are internally combined and initialize a device reset when  
driven low.  
INIT#  
Initialize  
These four pins are part of the mechanism that allows multiple  
FWH devices to be attached to the same bus. To identify the  
component, the correct strapping of these pins must be set. The  
boot device must have ID[3:0]=0000 and it is recommended that  
all subsequent devices should use sequential up-count strapping.  
These pins are internally pulled down with a resistor between 20-  
100 KΩ.  
ID[3:0]  
Identification Inputs  
IN  
X
These individual inputs can be used for additional board flexibility.  
The state of these pins can be read immediately at boot, through  
FWH internal registers. These inputs should be at their desired  
state before the start of the PCI clock cycle during which the read  
is attempted, and should remain in place until the end of the Read  
cycle. Unused FGPI pins must not be floated.  
General Purpose  
Inputs  
FGPI[4:0]  
TBL#  
IN  
IN  
X
X
To prevent any write operations to the Boot Block when driven low,  
regardless of the state of the block lock registers. When TBL# is  
high it disables hardware write protection for the top Boot Block.  
This pin cannot be left unconnected.  
Top Block Lock  
FWH[3:0]  
CLK  
FWH I/Os  
Clock  
I/O  
IN  
X
X
I/O Communications in FWH mode.  
To provide a clock input to the device. This pin is the same as that  
for the PCI clock and adheres to the PCI specifications.  
FWH4  
RST#  
FWH Input  
Reset  
IN  
IN  
X
X
Input communication in FWH mode.  
To reset the operation of the device  
X
When low, prevents any write operations to all but the highest  
addressable block. When WP# is high it disables hardware write  
protection for these blocks. This pin cannot be left unconnected.  
WP#  
Write Protect  
IN  
X
This pin determines whether the address pins are pointing to the  
row addresses or the column addresses in A/A Mux mode.  
R/C#  
RB#  
Row/Column Select  
Ready/Busy#  
IN  
X
X
To determine if the device is busy in write operations. Valid only in  
A/A Mux mode.  
OUT  
RES  
VDD  
VSS  
NC  
Reserved  
Power Supply  
Ground  
X
X
X
X
Reserved. These pins must be left unconnected.  
To provide power supply (3.0-3.6Volt).  
Circuit ground. All VSS pins must be grounded.  
Unconnected pins.  
PWR  
PWR  
X
X
X
No Connection  
1. IN=Input, OUT=output, I/O=Input/Output, PWR=Power  
(December, 2005, Version 1.0)  
4
AMIC Technology, Corp.  
12345678...32

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