Datasheet > A43E16161G-95F

A43E16161G-95F

更新时间： 2022-12-01 23:20:49

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
48页	557K
描述
Synchronous DRAM, 2MX16, 7ns, CMOS, PBGA54

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A43E16161G-95F 数据手册

A43E16161

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Version

Symbol

Parameter

Unit

Note

-75

-95

tRRD(min)

tRCD(min)

Row active to row active delay

RAS to

delay

CAS

tRP(min)

tRAS(min)

tRAS(max)

tRC(min)

Row precharge time

Row active time

μs

100

72.5

100

Row cycle time

tCDL(min)

tRDL(min)

tBDL(min)

tCCD(min)

Last data in new col. Address delay

Last data in row precharge

7.5

9.5

Last data in to burst stop

7.5

9.5

Col. Address to col. Address delay

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

PRELIMINARY (February, 2008, Version 0.3)

AMIC Technology, Corp.

1...5 6 789 10 11...48

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