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A43E16161G-95F PDF预览

A43E16161G-95F

更新时间: 2022-12-01 23:20:49
品牌 Logo 应用领域
联笙电子 - AMICC 动态存储器
页数 文件大小 规格书
48页 557K
描述
Synchronous DRAM, 2MX16, 7ns, CMOS, PBGA54

A43E16161G-95F 数据手册

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A43E16161  
Decoupling Capacitance Guide Line  
Recommended decoupling capacitance added to power line at board  
Parameter  
Symbol  
CDC1  
Value  
Unit  
μF  
Decoupling Capacitance between VDD and VSS  
Decoupling Capacitance between VDDQ and VSSQ  
0.1 + 0.01  
0.1 + 0.01  
CDC2  
μF  
Note: 1. VDD and VDDQ pins are separated each other.  
All VDD pins are connected in chip. All VDDQ pins are connected in chip.  
2. VSS and VSSQ pins are separated each other  
All VSS pins are connected in chip. All VSSQ pins are connected in chip.  
DC Electrical Characteristics  
(Recommended operating condition unless otherwise noted, TA = 0ºC to +70ºC for commercial or TA = -40ºC to +85ºC for extended)  
Speed  
Units Note  
Symbol  
Parameter  
Test Conditions  
-75  
-95  
Operating Current  
(One Bank Active)  
Burst Length = 1  
40  
Icc1  
mA  
mA  
1
tRC tRC(min), tCC tCC(min), IOL = 0mA  
CKE VIL(max), tCC = 15ns  
Icc2 P  
0.3  
0.5  
Precharge Standby Current  
in power-down mode  
Icc2 PS  
CKE VIL(max), tCC = ∞  
CKE VIH(min), CS VIH(min), tCC = 15ns  
Input signals are changed one time during 30ns  
ICC2N  
5.5  
Precharge Standby Current  
in non power-down mode  
mA  
mA  
CKE VIH(min), CLK VIL(max), tCC = ∞  
Input signals are stable.  
ICC2NS  
2
ICC3P  
ICC3N  
Active Standby current in  
non power-down mode  
(One Bank Active)  
1.5  
CKE VIL(max), tCC = 15ns  
CKE VIH(min),  
CS VIH(min), tCC = 15ns  
12  
45  
Input signals are changed one time during 30ns  
Operating Current  
(Burst Mode)  
IOL = 0mA, Page Burst  
All bank Activated, tCCD = tCCD (min)  
ICC4  
ICC5  
mA  
mA  
1
2
60  
Refresh Current  
tRC tRC (min)  
2 Banks  
100  
ICC6  
ICC7  
Self Refresh Current  
uA  
uA  
CKE 0.2V  
1 Banks  
80  
10  
Deep Power Down Current  
CKE 0.2V  
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).  
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).  
PRELIMINARY (February, 2008, Version 0.3)  
5
AMIC Technology, Corp.  

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