Datasheet > A43E16161G-95F

A43E16161G-95F

更新时间： 2022-12-01 23:20:49

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
48页	557K
描述
Synchronous DRAM, 2MX16, 7ns, CMOS, PBGA54

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A43E16161G-95F 数据手册

A43E16161

Mode Register Filed Table to Program Modes

Address

A10

Function

RFU

W.B.L

CAS Latency

Burst Length

(Note 3)

(Note 1)

(Note 2)

Test Mode

Type

CAS Latency

Burst Type

Burst Length

A8 A7

A6 A5 A4

Latency

Type

A2 A1 A0

BT=0

BT=1

Mode Register Set

Reserved

Sequential

Interleave

Vendor

Use

Only

Reserved

Reserved Reserved

512(Full) Reserved

Write Burst Length

Length

Burst

Single Bit

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

3. BA must be 0,0 to select the Mode Register (vs. the Extended Mode Register).

Extended Mode Register Table

A10

Address Bus (Ax)

↓

Bank

↓

PASR

↓

All have to be set to “0”

Up/Down

(Note)

Driver Strength

Partial-Array Self Refresh:

Driver Strength

Banks to be Self-Refreshed

Driver Strength

Full

3/4

1/2

1/4

All banks (Bank 0, 1)

Reserved

Bank 0

Reserved

All banks (Bank 0, 1)

Reserved

One bank (Bank 1)

Reserved

Note: BA must be 1 to select the Extended Mode Register (vs. the Mode Register)

PRELIMINARY (February, 2008, Version 0.3)

AMIC Technology, Corp.

1...7 8 91011 12 13...48

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