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A42MX09-2PQG100I PDF预览

A42MX09-2PQG100I

更新时间: 2024-10-28 19:15:27
品牌 Logo 应用领域
ACTEL 时钟可编程逻辑
页数 文件大小 规格书
123页 865K
描述
Field Programmable Gate Array, 336 CLBs, 14000 Gates, 146.3MHz, 684-Cell, CMOS, PQFP100, PLASTIC, QFP-100

A42MX09-2PQG100I 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:PLASTIC, QFP-100Reach Compliance Code:compliant
风险等级:5.74其他特性:CAN ALSO BE OPERATED AT 5.0V SUPPLY
最大时钟频率:146.3 MHzCLB-Max的组合延迟:1.8 ns
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm湿度敏感等级:3
可配置逻辑块数量:336等效关口数量:14000
输入次数:104逻辑单元数量:684
输出次数:104端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
组织:336 CLBS, 14000 GATES封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):245电源:3.3,3.3/5,5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:3.4 mm子类别:Field Programmable Gate Arrays
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

A42MX09-2PQG100I 数据手册

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v6.0  
40MX and 42MX FPGA Families  
Features  
HiRel Features  
Commercial, Industrial, Automotive, and Military  
Temperature Plastic Packages  
High Capacity  
Commercial, Military Temperature, and MIL-STD-883  
Ceramic Packages  
Single-Chip ASIC Alternative  
3,000 to 54,000 System Gates  
Up to 2.5 kbits Configurable Dual-Port SRAM  
Fast Wide-Decode Circuitry  
Up to 202 User-Programmable I/O Pins  
QML Certification  
Ceramic Devices Available to DSCC SMD  
Ease of Integration  
Mixed-Voltage Operation (5.0V or 3.3V for core and  
I/Os), with PCI-Compliant I/Os  
High Performance  
Up to 100% Resource Utilization and 100% Pin  
Locking  
5.6 ns Clock-to-Out  
250 MHz Performance  
5 ns Dual-Port SRAM Access  
100 MHz FIFOs  
Deterministic, User-Controllable Timing  
Unique In-System Diagnostic and Verification  
Capability with Silicon Explorer II  
7.5 ns 35-Bit Address Decode  
Low Power Consumption  
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing  
Product Profile  
Device  
A40MX02  
A40MX04  
A42MX09  
A42MX16  
A42MX24  
A42MX36  
Capacity  
System Gates  
SRAM Bits  
3,000  
6,000  
14,000  
24,000  
36,000  
54,000  
2,560  
Logic Modules  
Sequential  
Combinatorial  
Decode  
295  
547  
348  
336  
624  
608  
954  
912  
24  
1,230  
1,184  
24  
Clock-to-Out  
9.5 ns  
9.5 ns  
5.6 ns  
6.1 ns  
6.1 ns  
6.3 ns  
SRAM Modules  
(64x4 or 32x8)  
348  
516  
2
624  
928  
2
954  
1,410  
2
10  
1,230  
1,822  
6
Dedicated Flip-Flops  
Maximum Flip-Flops  
Clocks  
147  
1
273  
1
User I/O (maximum)  
PCI  
57  
69  
104  
140  
176  
Yes  
Yes  
202  
Yes  
Boundary Scan Test (BST)  
Yes  
Packages (by pin count)  
PLCC  
PQFP  
VQFP  
TQFP  
CQFP  
PBGA  
44, 68  
44, 68, 84  
84  
100, 160  
100  
176  
84  
84  
160, 208  
100  
80  
100  
80  
100, 160, 208  
208, 240  
100  
176  
176  
208, 256  
272  
January 2004  
i
© 2004 Actel Corporation  
See the Actel website (www.actel.com) for the latest version of this datasheet.  

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