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A42MX09-2PL84IX39 PDF预览

A42MX09-2PL84IX39

更新时间: 2024-10-28 13:32:39
品牌 Logo 应用领域
ACTEL 可编程逻辑
页数 文件大小 规格书
117页 2763K
描述
Field Programmable Gate Array, 684-Cell, CMOS, PQCC84,

A42MX09-2PL84IX39 技术参数

是否Rohs认证:不符合生命周期:Transferred
Reach Compliance Code:unknown风险等级:5.8
Is Samacsys:NJESD-30 代码:S-PQCC-J84
输入次数:104逻辑单元数量:684
输出次数:104端子数量:84
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:3.3,3.3/5,5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
子类别:Field Programmable Gate Arrays表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADBase Number Matches:1

A42MX09-2PL84IX39 数据手册

 浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第2页浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第3页浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第4页浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第5页浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第6页浏览型号A42MX09-2PL84IX39的Datasheet PDF文件第7页 
v 6 . 0  
40MX and 42MX FPGA Families  
F e a t u r e s  
H ig h C a p a c i t y  
Commercial, Military Temperature, and MIL-STD-883  
Ceramic Packages  
• Single-Chip ASIC Alternative  
• 3,000 to 54,000 System Gates  
QML Certification  
Up to 2.5 kbits Configurable Dual-Port SRAM  
• Fast Wide-Decode Circuitry  
Ceramic Devices Available to DSCC SMD  
E a s e o f I n t e g r a t io n  
Up to 202 User-Programmable I/O Pins  
Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os),  
with PCI-Compliant I/Os  
H ig h P e r f o r m a n c e  
• 5.6 ns Clock-to-Out  
Up to 100% Resource Utilization and 100% Pin Locking  
Deterministic, User-Controllable Timing  
• 250 MHz Performance  
• 5 ns Dual-Port SRAM Access  
• 100 MHz FIFOs  
Unique In-System Diagnostic and Verification Capability  
with Silicon Explorer II  
• 7.5 ns 35-Bit Address Decode  
Low Power Consumption  
H iR e l F e a t u r e s  
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing  
Commercial, Industrial, Automotive, and Military  
Temperature Plastic Packages  
P r o d u c t P r o f i l e  
Device  
A40MX02  
A40MX04  
A42MX09  
A42MX16  
A42MX24  
A42MX36  
Capacity  
System Gates  
SRAM Bits  
3,000  
6,000  
14,000  
24,000  
36,000  
54,000  
2,560  
Logic Modules  
Sequential  
Combinatorial  
Decode  
295  
547  
348  
336  
624  
608  
954  
912  
24  
1,230  
1,184  
24  
Clock-to-Out  
9.5 ns  
9.5 ns  
5.6 ns  
6.1 ns  
6.1 ns  
6.3 ns  
SRAM Modules  
(64x4 or 32x8)  
348  
516  
2
624  
928  
2
954  
1,410  
2
10  
1,230  
1,822  
6
Dedicated Flip-Flops  
Maximum Flip-Flops  
Clocks  
147  
1
273  
1
User I/O (maximum)  
PCI  
57  
69  
104  
140  
176  
Yes  
Yes  
202  
Yes  
Yes  
Boundary Scan Test (BST)  
Packages (by pin count))  
PLCC  
PQFP  
VQFP  
TQFP  
CQFP  
PBGA  
44, 68  
44, 68, 84  
84  
100, 160  
100  
176  
84  
84  
160, 208  
208, 240  
100  
80  
100  
80  
100, 160, 208  
100  
176  
176  
208, 256  
272  
J a n u a r y 2 0 0 4  
1
© 2004 Actel Corporation  

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