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A40MX04-3PLG84MX39 PDF预览

A40MX04-3PLG84MX39

更新时间: 2024-11-06 03:56:31
品牌 Logo 应用领域
ACTEL
页数 文件大小 规格书
115页 2797K
描述
Field Programmable Gate Array, 547-Cell, CMOS, PQCC84,

A40MX04-3PLG84MX39 数据手册

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5 . 1  
40MX and 42MX FPGA Families  
F e a t u r e s  
H ig h C a p a c i t y  
Commercial, Military Temperature and MIL-STD-883  
Ceramic Packages  
• Single-Chip ASIC Alternative  
• 3,000 to 54,000 System Gates  
QML Certification  
Up to 2.5 kbits Configurable Dual-Port SRAM  
• Fast Wide-Decode Circuitry  
Ceramic Devices Available to DSCC SMD  
E a s e o f I n t e g r a t io n  
Up to 202 User-Programmable I/O Pins  
Mixed Voltage Operation (5.0V or 3.3V I/O)  
H ig h P e r f o r m a n c e  
• 5.6 ns Clock-to-Out  
• Synthesis-Friendly Architecture to Support ASIC Design  
Methodologies  
• 250 MHz Performance  
• 5 ns Dual-Port SRAM Access  
• 100 MHz FIFOs  
Up to 100% Resource Utilization and 100% Pin Fixing  
Deterministic, User-Controllable Timing  
Unique In-System Diagnostic and Verification Capability  
with Silicon Explorer II  
• 7.5 ns 35-Bit Address Decode  
H iR e l F e a t u r e s  
Low Power Consumption  
Commercial, Industrial, and Military Temperature Plastic  
Packages  
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing  
• 5.0V and 3.3V Programmable PCI-Compliant I/O  
P r o d u c t P r o f i l e  
Device  
A40MX02  
A40MX04  
A42MX09  
A42MX16  
A42MX24  
A42MX36  
Capacity  
System Gates  
SRAM Bits  
3,000  
N/A  
6,000  
N/A  
14,000  
N/A  
24,000  
N/A  
36,000  
N/A  
54,000  
2,560  
Logic Modules  
Sequential  
Combinatorial  
Decode  
295  
547  
348  
336  
N/A  
624  
608  
N/A  
954  
912  
24  
1,230  
1,184  
24  
Clock-to-Out  
9.5 ns  
9.5 ns  
5.6 ns  
6.1 ns  
6.1 ns  
6.3 ns  
SRAM Modules  
(64x4 or 32x8)  
N/A  
N/A  
N/A  
348  
516  
2
N/A  
624  
928  
2
N/A  
954  
1,410  
2
10  
1,230  
1,822  
6
Dedicated Flip-Flops  
Maximum Flip-Flops  
Clocks  
147  
1
273  
1
User I/O (Maximum)  
PCI  
57  
No  
No  
69  
No  
No  
104  
No  
No  
140  
No  
No  
176  
Yes  
Yes  
202  
Yes  
Yes  
Boundary Scan Test (BST)  
Packages (by pin count)  
PLCC  
PQFP  
VQFP  
TQFP  
CQFP  
PBGA  
44, 68  
100  
80  
44, 68, 84  
84  
100, 160  
100  
176  
84  
84  
160, 208  
208, 240  
208, 256  
272  
100  
80  
100, 160, 208  
100  
176  
176  
O c t o b e r 2 0 0 3  
1
© 2003 Actel Corporation  

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