Datasheet > A40MX02-1VQG100YC

A40MX02-1VQG100YC

更新时间： 2024-11-12 04:02:43

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
142页	7428K
描述
FPGA

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数据手册

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A40MX02-1VQG100YC 数据手册

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Revision 11

40MX and 42MX FPGA Families

HiRel Features

Features

High Capacity

•

Commercial, Industrial, Automotive, and Military

Temperature Plastic Packages

•

Single-Chip ASIC Alternative

•

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

•

QML Certification

Ceramic Devices Available to DSCC SMD

Up to 202 User-Programmable I/O Pins

Ease of Integration

•

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

High Performance

•

5.6 ns Clock-to-Out

•

Up to 100% Resource Utilization and 100% Pin Locking

Deterministic, User-Controllable Timing

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

Unique In-System Diagnostic and Verification Capability

with Silicon Explorer II

7.5 ns 35-Bit Address Decode

•

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

Product Profile

Device

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

Capacity

System Gates

SRAM Bits

3,000

–

6,000

–

14,000

–

24,000

–

36,000

–

54,000

2,560

Logic Modules

Sequential

Combinatorial

Decode

–

295

–

547

–

348

336

–

624

608

–

954

912

1,230

1,184

Clock-to-Out

9.5 ns

5.6 ns

6.1 ns

6.3 ns

SRAM Modules

(64x4 or 32x8)

–

348

516

–

624

928

–

954

1,410

1,230

1,822

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

147

273

User I/O (maximum)

PCI

–

104

–

140

–

176

Yes

202

Yes

Boundary Scan Test (BST)

–

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

44, 68

44, 68, 84

100, 160

100

176

–

160, 208

–

208, 240

–

100

–

100

–

100, 160, 208

100

176

–

176

–

208, 256

272

–

May 2012

12 3 4 5 6 7...142

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