Datasheet > 可编程逻辑 > 现场可编程门阵列> A3PN015-1QNG68I

A3PN015-1QNG68I

更新时间： 2024-11-14 03:24:07

品牌	Logo	应用领域
ACTEL		栅现场可编程门阵列可编程逻辑
页数	文件大小	规格书
106页	3324K
描述
Field Programmable Gate Array, 384 CLBs, 15000 Gates, 384-Cell, CMOS, 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-68

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A3PN015-1QNG68I 数据手册

Revision 8

ProASIC3 nano Flash FPGAs

Advanced I/Os

Features and Benefits

•

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Wide Range of Features

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

•

10 k to 250 k System Gates

Up to 36 kbits of True Dual-Port SRAM

Up to 71 User I/Os

•

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

I/O Registers on Input, Output, and Enable Paths

Selectable Schmitt Trigger Inputs

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

Hot-Swappable and Cold-Sparing I/Os

•

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

†

•

Programmable Output Slew Rate and Drive Strength

Weak Pull-Up/-Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC3 Family

High Performance

•

350 MHz System Performance

Clock Conditioning Circuit (CCC) and PLL^†

In-System Programming (ISP) and Security

•

Up to Six CCC Blocks, One with an Integrated PLL

Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

•

Secure ISP Using On-Chip 128-Bit Advanced Encryption

†

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•

Wide Input Frequency Range (1.5 MHz to 350 MHz)

•

FlashLock to Secure FPGA Contents

Embedded Memory

Low Power

•

1 kbit of FlashROM User Nonvolatile Memory

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

•

Low Power ProASIC 3 nano Products

1.5 V Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

•

True Dual-Port SRAM (except ×18 organization)

Enhanced Commercial Temperature Range

High-Performance Routing Hierarchy

•

–20°C to +70°C

•

Segmented, Hierarchical Routing and Clock Structure

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices

ProASIC3 nano-Z Devices

System Gates

A3PN010

A3PN015

A3PN020

A3PN060 A3PN125 A3PN250

A3PN060Z A3PN125Z A3N250Z

A3PN030Z

10K

260

–

15K

128

384

–

20K

172

520

–

30K

256

768

–

60K

512

1,536

125K

1,024

3,072

250K

2,048

6,144

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

–

FlashROM Bits

1 k

–

1 k

–

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

–

QFN

VQFP

QN48

QN68

QN48, QN68

VQ100

Notes:

1. A3PN030 is available in the Z feature grade only.

2. A3PN030 and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E handbooks.

† A3PN030 and smaller devices do not support this feature.

April 2010

12 3 4 5 6 7...106

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与A3PN015-1QNG68I相关器件

型号	品牌	获取价格	描述	数据表
A3PN0151VQ100	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100ES	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100I	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100PP	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100Y	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100YES	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100YI	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQ100YPP	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQG100	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs
A3PN0151VQG100ES	MICROSEMI	获取价格	ProASIC3 nano Flash FPGAs

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