Advanced v0.2
™
ProASIC3E Flash Family FPGAs
Pro (Professional) I/O
Features and Benefits
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700 Mbps DDR, LVDS-Capable I/Os
High Capacity
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL and LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V,
GTL 2.5 V / 3.3 V, HSTL Class 1 and 2, SSTL2 Class 1 and 2,
SSTL3 Class 1 and 2
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600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
Reprogrammable Flash Technology
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130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
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Live-At-Power-Up Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered-Off
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I/O Registers on Input, Output, and Enable Paths
Hot-Swappable I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay, Weak Pull-Up/Down
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
On-Chip User Nonvolatile Memory
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1 kbit of FlashROM (FROM)
Performance
IEEE1149.1 (JTAG) Boundary-Scan Test
Pin-Compatible Packages Across the ProASIC3E Family
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150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI
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Up to 350 MHz External System Performance
Clock Conditioning Circuit (CCC) and PLL
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Six CCC Blocks, Each with an Integrated PLL
Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
In-System Programming (ISP) and Security
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Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant)
FlashLock™ to Secure FPGA Contents
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Wide Input Frequency Range (1.5 MHz to 350 MHz)
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SRAMs and FIFOs
Low Power
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Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
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1.5 V Core Voltage for Low Power
x9, x18 Organizations Available)
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
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True Dual-Port SRAM (except x18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
High-Performance Routing Hierarchy
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Programmable Embedded FIFO Control Logic
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Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Table 1 •
ProASIC3E Product Family
A3PE600
600 k
13,824
108
24
A3PE1500
A3PE3000
System Gates
1.5 M
38,400
270
60
1 k
Yes
6
3 M
75,264
504
112
1 k
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
1 k
Yes
Yes
6
1
6
CCCs with Integrated PLLs
2
18
18
18
VersaNet Globals
I/O Banks
8
8
8
Maximum User I/Os
270
439
616
Package Pins
PQFP
PQ208
FG256, FG484
PQ208
FG484, FG676
PQ208
FG484, FG896
FBGA
Notes:
1. The PQ208 package has six CCCs and two PLLs.
2. Six chip (main) and three quadrant global networks are available.
3. For devices supporting lower densities, refer to the ProASIC3 Flash FPGAs datasheet.
January 2005
i
© 2005 Actel Corporation
See Actel’s website for the latest version of the datasheet.