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A3PE3000-FFGG896 PDF预览

A3PE3000-FFGG896

更新时间: 2024-09-21 06:34:55
品牌 Logo 应用领域
ACTEL 现场可编程门阵列闪存可编程逻辑时钟
页数 文件大小 规格书
152页 5016K
描述
ProASIC3E Flash Family FPGAs

A3PE3000-FFGG896 技术参数

是否Rohs认证:符合生命周期:Transferred
包装说明:31 X 31 MM, 2.23 MM HEIGHT, 1 MM PITCH, GREEN, FBGA-896Reach Compliance Code:compliant
风险等级:5.76Is Samacsys:N
最大时钟频率:350 MHzJESD-30 代码:S-PBGA-B896
JESD-609代码:e1长度:31 mm
湿度敏感等级:3可配置逻辑块数量:75264
等效关口数量:3000000输入次数:620
逻辑单元数量:75264输出次数:620
端子数量:896最高工作温度:70 °C
最低工作温度:组织:75264 CLBS, 3000000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA896,30X30,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):250
电源:1.5/3.3 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2.44 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.575 V
最小供电电压:1.425 V标称供电电压:1.5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:31 mmBase Number Matches:1

A3PE3000-FFGG896 数据手册

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v1.0  
®
ProASIC3E Flash Family FPGAs  
with Optional Soft ARM Support  
®
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
Features and Benefits  
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS  
2.5 V / 5.0 V Input  
High Capacity  
• 600 k to 3 Million System Gates  
• 108 to 504 kbits of True Dual-Port SRAM  
• Up to 620 User I/Os  
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
Reprogrammable Flash Technology  
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process  
• Live at Power-Up (LAPU) Level 0 Support  
• Single-Chip Solution  
• I/O Registers on Input, Output, and Enable Paths  
• Hot-Swappable and Cold Sparing I/Os  
• Programmable Output Slew Rate and Drive Strength  
• Programmable Input Delay  
• Retains Programmed Design when Powered Off  
On-Chip User Nonvolatile Memory  
High1 kPbeitroffoFrlmashaRnOcMewith Synchronous Interfacing  
• Schmitt Trigger Option on Single-Ended Inputs  
• Weak Pull-Up/-Down  
• 350 MHz System Performance  
• IEEE 1149.1 (JTAG) Boundary Scan Test  
• 3.3 V, 66 MHz 64-Bit PCI  
®
• Pin-Compatible Packages across the ProASIC 3E Family  
In-System Programming (ISP) and Security  
• Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
Clock Conditioning Circuit (CCC) and PLL  
• Six CCC Blocks, Each with an Integrated PLL  
®
• Configurable  
Phase-Shift,  
Multiply/Divide,  
Delay  
• FlashLock to Secure FPGA Contents  
Capabilities and External Feedback  
Low Power  
• Wide Input Frequency Range (1.5 MHz to 200 MHz)  
• Core Voltage for Low Power  
• Support for 1.5-V-Only Systems  
SRAMs and FIFOs  
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
HighLo-wPe-ImrfpoerdmanacenFcleashRoSwuittcinhegs Hierarchy  
• Segmented, Hierarchical Routing and Clock Structure  
• Ultra-Fast Local and Long-Line Network  
• True Dual-Port SRAM (except ×18)  
• 24 SRAM and FIFO Configurations with Synchronous  
Operation up to 350 MHz  
• Enhanced High-Speed, Very-Long-Line Network  
• High-Performance, Low-Skew Global Network  
• Architecture Supports Ultra-High Utilization  
ARM® Processor Support in ProASIC3E FPGAs  
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available  
with or without Debug  
Pro (Professional) I/O  
• 700 Mbps DDR, LVDS-Capable I/Os  
Table 1-1 • ProASIC3E Product Family  
ProASIC3E Devices  
Cortex-M1 Devices  
System Gates  
A3PE600  
A3PE1500  
A3PE3000  
1
M1A3PE1500  
M1A3PE3000  
600 k  
13,824  
108  
24  
1.5 M  
38,400  
270  
60  
3 M  
75,264  
504  
112  
1 k  
VersaTiles (D-flip-flops)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
FlashROM Bits  
1 k  
1 k  
Secure (AES) ISP  
Yes  
6
Yes  
6
Yes  
6
2
CCCs with Integrated PLLs  
3
VersaNet Globals  
18  
18  
18  
I/O Banks  
8
8
8
Maximum User I/Os  
270  
444  
620  
Package Pins  
PQFP  
FBGA  
PQ208  
FG256, FG484  
PQ208  
FG484, FG676  
PQ208  
FG324, FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. The PQ208 package has six CCCs and two PLLs.  
3. Six chip (main) and three quadrant global networks are available.  
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.  
March 2008  
I
© 2008 Actel Corporation  

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