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A3PE3000-1PQ208

更新时间： 2024-11-10 12:41:15

品牌	Logo	应用领域
美高森美 - MICROSEMI		现场可编程门阵列闪存可编程逻辑栅时钟
页数	文件大小	规格书
162页	8630K
描述
ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

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技术参数
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A3PE3000-1PQ208 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	FQFP, QFP208,1.2SQ,20	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.65
最大时钟频率：	350 MHz	JESD-30 代码：	S-PQFP-G208
JESD-609代码：	e0	长度：	28 mm
湿度敏感等级：	3	可配置逻辑块数量：	75264
等效关口数量：	3000000	输入次数：	147
逻辑单元数量：	75264	输出次数：	147
端子数量：	208	最高工作温度：	70 °C
最低工作温度：		组织：	75264 CLBS, 3000000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装等效代码：	QFP208,1.2SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	峰值回流温度（摄氏度）：	225
电源：	1.5/3.3 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	4.1 mm
子类别：	Field Programmable Gate Arrays	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	28 mm	Base Number Matches：	1

A3PE3000-1PQ208 数据手册

Revision 13

ProASIC3E Flash Family FPGAs

with Optional Soft ARM Support

Features and Benefits

Pro (Professional) I/O

•

700 Mbps DDR, LVDS-Capable I/Os

High Capacity

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

•

600 k to 3 Million System Gates

108 to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

Reprogrammable Flash Technology

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

•

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

•

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/-Down

On-Chip User Nonvolatile Memory

•

1 kbit of FlashROM with Synchronous Interfacing

High Performance

•

350 MHz System Performance

3.3 V, 66 MHz 64-Bit PCI

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC 3E Family

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

Clock Conditioning Circuit (CCC) and PLL

•

FlashLock Designed to Secure FPGA Contents

•

Six CCC Blocks, Each with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay Capabilities

and External Feedback

Low Power

•

Core Voltage for Low Power

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

•

Wide Input Frequency Range (1.5 MHz to 350 MHz)

SRAMs and FIFOs

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

High-Performance Routing Hierarchy

•

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

•

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous Operation

up to 350 MHz

ARM^®Processor Support in ProASIC3E FPGAs

•

M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices

A3PE600

A3PE1500

A3PE3000

Cortex-M1 Devices

M1A3PE1500

M1A3PE3000

System Gates

600,000

13,824

108

1,500,000

3,000,000

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

38,400

270

75,264

504

112

FlashROM Kbits

Secure (AES) ISP

Yes

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

270

444

620

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. The PQ208 package supports six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.

January 2013

12 3 4 5 6 7...162

中文翻译

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与A3PE3000-1PQ208相关器件

型号	品牌	获取价格	描述	数据表
A3PE3000-1PQ208ES	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208I	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208PP	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208Y	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208YC	MICROSEMI	获取价格	FPGA
A3PE3000-1PQ208YES	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208YI	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ208YPP	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ484	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
A3PE3000-1PQ484ES	MICROSEMI	获取价格	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

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