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A3PE1500-2FGG896PP PDF预览

A3PE1500-2FGG896PP

更新时间: 2024-09-21 06:34:55
品牌 Logo 应用领域
ACTEL 闪存
页数 文件大小 规格书
152页 5016K
描述
ProASIC3E Flash Family FPGAs

A3PE1500-2FGG896PP 数据手册

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v1.0  
®
ProASIC3E Flash Family FPGAs  
with Optional Soft ARM Support  
®
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
Features and Benefits  
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS  
2.5 V / 5.0 V Input  
High Capacity  
• 600 k to 3 Million System Gates  
• 108 to 504 kbits of True Dual-Port SRAM  
• Up to 620 User I/Os  
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
Reprogrammable Flash Technology  
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process  
• Live at Power-Up (LAPU) Level 0 Support  
• Single-Chip Solution  
• I/O Registers on Input, Output, and Enable Paths  
• Hot-Swappable and Cold Sparing I/Os  
• Programmable Output Slew Rate and Drive Strength  
• Programmable Input Delay  
• Retains Programmed Design when Powered Off  
On-Chip User Nonvolatile Memory  
High1 kPbeitroffoFrlmashaRnOcMewith Synchronous Interfacing  
• Schmitt Trigger Option on Single-Ended Inputs  
• Weak Pull-Up/-Down  
• 350 MHz System Performance  
• IEEE 1149.1 (JTAG) Boundary Scan Test  
• 3.3 V, 66 MHz 64-Bit PCI  
®
• Pin-Compatible Packages across the ProASIC 3E Family  
In-System Programming (ISP) and Security  
• Secure ISP Using On-Chip 128-Bit Advanced Encryption  
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)  
Clock Conditioning Circuit (CCC) and PLL  
• Six CCC Blocks, Each with an Integrated PLL  
®
• Configurable  
Phase-Shift,  
Multiply/Divide,  
Delay  
• FlashLock to Secure FPGA Contents  
Capabilities and External Feedback  
Low Power  
• Wide Input Frequency Range (1.5 MHz to 200 MHz)  
• Core Voltage for Low Power  
• Support for 1.5-V-Only Systems  
SRAMs and FIFOs  
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
HighLo-wPe-ImrfpoerdmanacenFcleashRoSwuittcinhegs Hierarchy  
• Segmented, Hierarchical Routing and Clock Structure  
• Ultra-Fast Local and Long-Line Network  
• True Dual-Port SRAM (except ×18)  
• 24 SRAM and FIFO Configurations with Synchronous  
Operation up to 350 MHz  
• Enhanced High-Speed, Very-Long-Line Network  
• High-Performance, Low-Skew Global Network  
• Architecture Supports Ultra-High Utilization  
ARM® Processor Support in ProASIC3E FPGAs  
• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available  
with or without Debug  
Pro (Professional) I/O  
• 700 Mbps DDR, LVDS-Capable I/Os  
Table 1-1 • ProASIC3E Product Family  
ProASIC3E Devices  
Cortex-M1 Devices  
System Gates  
A3PE600  
A3PE1500  
A3PE3000  
1
M1A3PE1500  
M1A3PE3000  
600 k  
13,824  
108  
24  
1.5 M  
38,400  
270  
60  
3 M  
75,264  
504  
112  
1 k  
VersaTiles (D-flip-flops)  
RAM kbits (1,024 bits)  
4,608-Bit Blocks  
FlashROM Bits  
1 k  
1 k  
Secure (AES) ISP  
Yes  
6
Yes  
6
Yes  
6
2
CCCs with Integrated PLLs  
3
VersaNet Globals  
18  
18  
18  
I/O Banks  
8
8
8
Maximum User I/Os  
270  
444  
620  
Package Pins  
PQFP  
FBGA  
PQ208  
FG256, FG484  
PQ208  
FG484, FG676  
PQ208  
FG324, FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. The PQ208 package has six CCCs and two PLLs.  
3. Six chip (main) and three quadrant global networks are available.  
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.  
March 2008  
I
© 2008 Actel Corporation  

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