Datasheet > A3P030-2QN48I

A3P030-2QN48I

更新时间： 2024-11-07 03:00:47

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
221页	6478K
描述
Field Programmable Gate Array, 768 CLBs, 30000 Gates, CMOS

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技术参数
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A3P030-2QN48I 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	HQCCN,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.25
JESD-30 代码：	S-XQCC-N48	长度：	6 mm
可配置逻辑块数量：	768	等效关口数量：	30000
端子数量：	48	最高工作温度：	100 °C
最低工作温度：	-40 °C	组织：	768 CLBS, 30000 GATES
封装主体材料：	UNSPECIFIED	封装代码：	HQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG
峰值回流温度（摄氏度）：	235	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	最大供电电压：	1.575 V
最小供电电压：	1.425 V	标称供电电压：	1.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	6 mm
Base Number Matches：	1

A3P030-2QN48I 数据手册

Revision 18

DS0097

ProASIC3 Flash Family FPGAs

with Optional Soft ARM Support

Advanced I/O

Features and Benefits

•

700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

High Capacity

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

•

15 K to 1 M System Gates

Up to 144 Kbits of True Dual-Port SRAM

Up to 300 User I/Os

•

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

Reprogrammable Flash Technology

†

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

2.5 V / 5.0 V Input

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS (A3P250 and above)

•

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

•

I/O Registers on Input, Output, and Enable Paths

‡

Hot-Swappable and Cold Sparing I/Os

High Performance

†

Programmable Output Slew Rate and Drive Strength

•

350 MHz System Performance

Weak Pull-Up/-Down

†

3.3 V, 66 MHz 64-Bit PCI

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC3 Family

In-System Programming (ISP) and Security

Clock Conditioning Circuit (CCC) and PLL^†

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM -enabled ProASIC 3 devices)

•

Six CCC Blocks, One with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay Capabilities

and External Feedback

†

via JTAG (IEEE 1532–compliant)

•

FlashLock to Secure FPGA Contents

Low Power

•

Wide Input Frequency Range (1.5 MHz to 350 MHz)

Embedded Memory^†

•

Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

•

1 Kbit of FlashROM User Nonvolatile Memory

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

†

High-Performance Routing Hierarchy

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

•

Segmented, Hierarchical Routing and Clock Structure

•

True Dual-Port SRAM (except ×18)

ARM Processor Support in ProASIC3 FPGAs

•

M1 ProASIC3 Devices—ARM Cortex -M1 Soft Processor

Available with or without Debug

ProASIC3 Devices

Cortex-M1 Devices

System Gates

A3P015

A3P030

A3P060 A3P125

A3P250

A3P400

A3P600

A3P1000

M1A3P250 M1A3P400

M1A3P600 M1A3P1000

15,000

30,000

60,000 125,000

250,000

400,000

600,000

1,000,000

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

128

384

–

256

768

–

512

1,536

1,024

3,072

2,048

6,144

–

9,216

–

13,824

108

–

24,576

144

–

FlashROM Kbits

Secure (AES) ISP

–

Yes

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

157

194

235

300

Notes:

1. A3P015 is not recommended for new designs.

2. Refer to the Cortex-M1 product brief for more information.

3. AES is not available for Cortex-M1 ProASIC3 devices.

4. Six chip (main) and three quadrant global networks are available for A3P060 and above.

5. The M1A3P250 device does not support this package.

6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.

7. Package not available.

† A3P015 and A3P030 devices do not support this feature.

‡ Supported only by A3P015 and A3P030 devices.

March 2016

12 3 4 5 6 7...221

中文翻译

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与A3P030-2QN48I相关器件

型号	品牌	获取价格	描述	数据表
A3P030-2QN48IY	MICROSEMI	获取价格	Field Programmable Gate Array,
A3P030-2QN48Y	MICROSEMI	获取价格	FPGA, 768 CLBS, 30000 GATES, QCC48, 6 X 6 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, QFP-48
A3P030-2QN68	MICROSEMI	获取价格	Field Programmable Gate Array, 768 CLBs, 30000 Gates, 350MHz, CMOS, 8 X 8 MM, 0.90 MM HEIG
A3P030-2QN68I	MICROSEMI	获取价格	Field Programmable Gate Array, 768 CLBs, 30000 Gates, CMOS
A3P030-2QN68IY	MICROSEMI	获取价格	Field Programmable Gate Array,
A3P030-2QN68Y	MICROSEMI	获取价格	FPGA, 768 CLBS, 30000 GATES, QCC68, 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, QFP-68
A3P030-2QNG100	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P030-2QNG100ES	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P030-2QNG100I	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
A3P030-2QNG100PP	MICROSEMI	获取价格	ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

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