DMOS Dual Full-Bridge
Microstepping PWM Motor Driver
A3992
Synchronous Rectification. When a PWM off-cycle with the two serial port control bits:
1. Active mode. Prevents reversal of load current.
is triggered, by a bridge disable command or internal
fixed off-time cycle, load current recirculates accord-
ing to the decay mode selected by control logic. The
A3992 synchronous rectification feature turns on the
appropriate MOSFETs during current decay, and effec-
tively shorts out the body diodes with the low RDS(on)
driver. This lowers power dissipation significantly, and
can eliminate the need for external Schottky diodes for
most applications.
Turns off synchronous rectification when a 0 current
level is detected.
2. Passive mode. Allows reversal of current, but will
turn off the synchronous rectifier circuit if the load
current inversion ramps up to the current limit.
3. Disabled. Prevents MOSFET switching during load
recirculation in fast decay portion of the off-time. Dur-
ing the slow decay portion of the off-time, the low-side
switch turns on, which recirculates current through the
low-side MOSFET and low-side body diode.
Three distinct modes of operation can be configured
Applications Notes
Current Sensing. To minimize inaccuracies in sens-
ing the IPEAK current level caused by ground trace I•R
drops, the sense resistor should have an independent
ground return to the GND terminal of the device. For
low value sense resistors, the I•R drops in the PCB
sense resistor traces can be significant and should
be taken into account. The use of sockets should
be avoided because they can introduce variation in
Thermal Protection. Circuitry turns off all drivers
when the junction temperature reaches 165°C typical.
It is intended only to protect the device from failures
due to excessive junction temperatures, and should not
imply that output short circuits are permitted. Thermal
shutdown has a hysteresis of approximately 15°C.
Serial Port Write Timing Operation. Data is clocked
into a shift register on the rising edge of a CLOCK
signal. Normally, STROBE is held high, and is only
brought low to initiate a write cycle. The data is writ-
ten MSB first. Refer to the diagram below for timing
requirements.
RSENSE due to their contact resistance.
Allegro MicroSystems recommends a value of RSENSE
given by:
R
SENSE = 0.5 / ITRIP MAX
.
F
D
E
STROBE
C
CLOCK
G
DATA
MSB
LSB - D0
B
A
SLEEP
H
Serial Port Timing Diagram
A. Minimum Data Setup Time
B. Minimum Data Hold Time
C. Minimum Setup Strobe to Clock rising edge
D. Minimum Clock High Pulse Width
E. Minimum Clock Low Pulse Width
15 ns F. Minimum Setup Clock rising edge to Strobe
10 ns G. Minimum Strobe Pulse Width
120 ns H. Minimum Sleep to Clock Setup Time
40 ns I. Setup “Idle” Release to Output Enable
40 ns
50 ns
120 ns
50 μs
1 ms
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com