A3992SBT-

更新时间： 2024-01-31 11:02:21

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器电机
页数	文件大小	规格书
13页	477K
描述
DMOS Dual Full-Bridge Microstepping PWM Motor Driver

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技术参数
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A3992SBT- 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	HTSSOP, TSSOP24,.25	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.13
Is Samacsys：	N	其他特性：	ALSO REQUIRES 15V TO 50V VBB SUPPLY
模拟集成电路 - 其他类型：	STEPPER MOTOR CONTROLLER	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	7.8 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-20 °C	最大输出电流：	1.5 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTSSOP
封装等效代码：	TSSOP24,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	50 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Motion Control Electronics
最大供电电流 (Isup)：	12 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	NMOS
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm	Base Number Matches：	1

A3992SBT- 数据手册

DMOS Dual Full-Bridge

Microstepping PWM Motor Driver

A3992

D14 – D15 Synchronous Rectiﬁcation. 2 bits set the D16, D17 (Reserved). 2 bits reserved for testing.

different modes of operation (see Synchronous Rectiﬁ-

cation in the Functional Description section):

They should be programmed to 0 during normal op-

eration.

D15

D14

Synchronous Rectifier

Active

D18 Idle Mode. The device can be put into the low-

power Idle mode by writing a 0 to D18. The outputs

are disabled, the charge pump turned off, and the de-

vice consumes a lower supply current. The undervolt-

age monitor circuit remains active.

Disabled

Passive

Allegro defined use

Functional Description

PWM signals to the control block. In mixed decay

mode, the ﬁrst portion of the off-time operates in fast

decay, until the fast decay time count is reached, fol-

lowed by slow decay for the remainder of the ﬁxed

off-time. If the fast decay time is set longer than the off-

time, the device effectively operates in fast decay mode.

VREG. The VREG pin should be decoupled with a

0.22 μF capacitor to ground. This internally gener-

ated supply voltage is used to run the sink side DMOS

outputs. VREG is internally monitored and in the

case of a fault condition, the outputs of the device are

disabled.

Current Regulation. The reference voltage can be set

by analog input to the REF terminal, or via the internal

2 V precision reference. The choice of reference volt-

age and selection of sense resistor set maximum trip

current, as follows:

Oscillator. The PWM timer is based on an oscillator

input, typically 4 MHz. The A3992 can be conﬁgured

to select either the 4 MHz internal oscillator or, if

more precise accuracy is required, an external clock

can be connected to the OSC terminal. If an external

clock is used, 3 internal divider choices are selectable

via the serial port to allow ﬂexibility in choosing f_OSC

based on available system clocks. If the internal oscil-

lator option is used, the absolute accuracy is dependent

on process variation of resistance and capacitance.

A precision resistor can be connected from the OSC

terminal to V_DDto further improve the tolerance. The

frequency is calculated as:

I_TRIPMAX= V_REF/(Range × R_SENSE) .

Microstepping current levels are set according to the

following equations:

I_TRIP= V_DAC/(Range × R_SENSE) , and

V_DAC= ((1+DAC) × V_REF)/64 ,

where DAC is the input code, 1 to 63 (Word 0, D1 to

D12), and Range is 4 or 8, as selected by Word 0, D18.

Programming a DAC input code to 0 disables the cor-

responding bridge, and results in minimum load current.

_OSC= 204 × 10⁹/R_OSC

If the internal oscillator is used without the external re-

sistor the OSC terminal should be connected to GND.

PWM Timer Function. The PWM timer is program-

mable via the serial port to provide ﬁxed off-time

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1...4 5 678 9 10...13

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