A3955
Full-Bridge PWM Microstepping Motor Driver
Note the A3955SB (DIP) and the A3955SLB
(SOIC) are electrically identical and share a
common terminal number assignment.
Terminal Functions
Terminal
Name
PFD
Description
1
2
(Percent Fast Decay) The analog input used to set the current-decay mode.
REF
(VREF) The voltage at this input (along with the value of RS and the states of DAC inputs
D0, D1, and D2) set the peak output current.
3
RC
The parallel combination of external resistor RT and capacitor CT set the off time for the
PWM current regulator. CT also sets the blanking time.
4-5
GROUND
Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
6
7
LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V.
PHASE
D2
The PHASE input determines the direction of current in the load.
(DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter.
(DATA1) One-of-three control bits for the internal digital-to-analog converter.
One-of-two output load connections.
8
9
D1
10
11
OUTA
SENSE
Connection to the sink-transistor emitters. Sense resistor RS is connected between this
point and ground.
12-13
GROUND
Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
14
15
16
D0
(DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter.
One-of-two output load connections.
OUTB
LOAD SUPPLY (VBB) Supply voltage for the load.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com