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A3958SLBTR PDF预览

A3958SLBTR

更新时间: 2024-01-12 13:02:55
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器电机
页数 文件大小 规格书
10页 380K
描述
DMOS Full-Bridge PWM Motor Driver

A3958SLBTR 数据手册

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A3958  
DMOS Full-Bridge PWM Motor Driver  
Features and Benefits  
±2 A, 50 V continuous output rating  
Low rDS(on) outputs (270 mΩ, typical)  
Description  
Designed for pulse width modulated (PWM) current control of  
DC motors, theA3958 is capable of continuous output currents  
Programmable mixed, fast, and slow current-decay modes  
Serial interface controls chip functions  
Synchronous rectification for low power dissipation  
Internal UVLO and thermal-shutdown circuitry  
Crossover-current protection  
to ±2 A and operating voltages to 50 V. Internal fixed off-time  
PWM current-control timing circuitry can be programmed via  
a serial interface to operate in slow, fast, and mixed current-  
decay modes.  
PHASE and ENABLE input terminals are provided for use  
in controlling the speed and direction of a DC motor with  
externally applied PWM-control signals. The ENABLE input  
can be programmed via the serial port to PWM the bridge in  
fast or slow current decay. Internal synchronous rectification  
control circuitry is provided to reduce power dissipation during  
PWM operation.  
Packages:  
Internal circuit protection includes thermal shutdown with  
hysteresis, and crossover-current protection. Special power-up  
sequencing is not required.  
Package B, 24-pin DIP  
with exposed tabs  
The A3958 is supplied in a choice of two power packages, a  
24-pin plastic DIP with exposed thermal tabs (package suffix  
‘B’), and a 24-pin SOIC with internally fused pins (package  
suffixLB’).Inbothcases,thepowerpinsareatgroundpotential  
and need no electrical isolation. Each package type is lead (Pb)  
free, with 100% matte tin leadframe.  
Package LB, 24-pin SOIC  
with internally fused pins  
Not to scale  
Functional Block Diagram  
V
BB  
VDD  
+
LOGIC  
SUPPLY  
LOAD  
SUPPLY  
CHARGE PUMP  
BANDGAP  
VREG  
CHARGE  
PUMP  
UNDER-  
VOLTAGE &  
BANDGAP  
REGULATOR  
VDD  
FAULT DETECT  
CREG  
TSD  
CONTROL LOGIC  
OUT  
A
B
MODE  
PHASE  
ENABLE  
OUT  
SENSE  
CS  
ZERO  
CURRENT  
DETECT  
FIXED OFF  
RS  
BLANK  
DECAY  
OSC  
PROGRAMMABLE  
PWM TIMER  
CURRENT  
SENSE  
SLEEP  
MODE  
CLOCK  
DATA  
STROBE  
REFERENCE  
BUFFER &  
DIVIDER  
SERIAL  
PORT  
RANGE  
REF  
VREF  
RANGE  
Dwg. FP-048  
29319.31F  

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