A3958SLBTR

更新时间： 2024-01-07 17:33:11

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器电机
页数	文件大小	规格书
10页	380K
描述
DMOS Full-Bridge PWM Motor Driver

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A3958SLBTR 数据手册

A3958

DMOS Full-Bridge PWM Motor Driver

FUNCTIONAL DESCRIPTION (continued)

D15 Phase Logic. Bit D15, in conjunction with PHASE,

determines if the device is operating in the forward

(PHASE ≠ D15) or reverse (PHASE = D15) state.

D18 Test Mode. Bit D18 low (default) operates the

device in normal mode. D18 is only used for testing

purposes. The user should never change this bit.

PHASE D15 State

OUT_AOUT_B

D19 Sleep Mode. Bit D19 selects a Sleep mode to

minimize power consumption when not in use. This

disables much of the internal circuitry including the

regulator and charge pump. On power up the serial port is

initialized to all 0s. Bit D19 should be programmed high

for 1 ms before attempting to enable any output driver.

Reverse

Forward

Reverse

Low

High

Low

High

Low

High

D16 G_mRange Select. Bit D16, in conjunction with

RANGE, determines if V_REFis divided by 5 (RANGE ≠

D16) or by 10 (RANGE = D16).

D19

Sleep Mode

Sleep

Normal

RANGE

D16

Divider

Serial Port Write Timing Operation. Data is clocked

into the shift register on the rising edge of the CLOCK

signal. Normally STROBE will be held high, only brought

low to initiate a write cycle. Refer to diagram below and

these speciﬁcations for the minimum timing requirements.

A. DATA setup time ........................................... 15 ns

B. DATA hold time ............................................ 10 ns

C. Setup STROBE to CLOCK rising edge ........ 50 ns

D. CLOCK high pulse width ............................. 50 ns

E. CLOCK low pulse width ............................... 50 ns

F. Setup CLOCK rising edge to STROBE ........ 50 ns

G. STROBE pulse width ................................... 50 ns

÷10

÷5

÷10

D17 Internal PWM Mode. Bit D17, in conjunction with

MODE, selects slow (MODE ≠ D17) or mixed (MODE =

D17) current decay.

MODE D17 Current-Decay Mode

Mixed

Slow

Mixed

V_REG. This internally generated voltage is used to operate

the sink-side DMOS outputs. The V_REGterminal should

be decoupled with a 0.22 μF capacitor to ground. V_REGis

Serial Port Write Timing

STROBE

CLOCK

D19

D18

DATA

Dwg. WP-038

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

1...3 4 567 8 9 10

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