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A32300DXV-RQ240CX79 PDF预览

A32300DXV-RQ240CX79

更新时间： 2024-11-06 14:06:47
品牌 Logo 应用领域
ACTEL 栅可编程逻辑
页数 文件大小 规格书
84页 2085K
描述
Field Programmable Gate Array, 3721-Cell, CMOS, PQFP240,

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A32300DXV-RQ240CX79 技术参数

是否Rohs认证：符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：NJESD-30 代码：S-PQFP-G240
湿度敏感等级：4输入次数：202
逻辑单元数量：3721输出次数：202
端子数量：240最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：HLFQFP封装等效代码：HQFP240,1.37SQ,20
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
电源：3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified子类别：Field Programmable Gate Arrays
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUADBase Number Matches：1

A32300DXV-RQ240CX79 数据手册

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v3.0  
Integrator Series FPGAs:  
1200XL and 3200DX Families  
Features  
General Description  
Actel’s Integrator Series FPGAs are the first programmable  
logic devices optimized for high-speed system logic  
integration. Based on Actel’s proprietary antifuse  
technology and 0.6-micron double metal CMOS process,  
Integrator Series devices offer a fine-grained, register-rich  
architecture with embedded dual-port SRAM and  
wide-decode circuitry.  
High Capacity  
• 2,500 to 30,000 Logic Gates  
• Up to 3Kbits Configurable Dual-Port SRAM  
• Fast Wide-Decode Circuitry  
• Up to 250 User-Programmable I/O Pins  
High Performance  
• 225 MHz Performance  
• 5 ns Dual-Port SRAM Access  
• 100 MHz FIFOs  
Integrator Series’ 3200DX and 1200XL families were  
designed to integrate system logic which is typically  
implemented in multiple CPLDs, PALs, and FPGAs. These  
devices provide the features and performance required for  
today’s complex, high-speed digital logic systems. The  
3200DX family offers fast dual-port SRAM for implementing  
FIFOs, LIFOs, and temporary data storage. The large  
number of storage elements can efficiently address  
applications requiring wide datapath manipulation and  
transformation functions such as telecommunications,  
networking, and DSP.  
• 7.5 ns 35-Bit Address Decode  
Ease-of-Integration  
• Synthesis-Friendly Architecture Supports ASIC Design  
Methodologies.  
• 95–100% Device Utilization using Automatic  
Place-and-Route Tools.  
• Deterministic, User-Controllable Timing Via Timing  
Driven Software Tools with Up To 100% Pin Fixing.  
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.  
Integrator Series Product Profile Family  
1200XL  
3200DX  
Device  
A1225XL  
A1240XL  
A1280XL  
A3265DX  
A32100DX  
A32140DX  
A32200DX  
A32300DX  
Capacity  
Logic Gates  
SRAM Bits  
1
2,500  
N/A  
4,000  
N/A  
8,000  
N/A  
6,500  
N/A  
10,000  
2,048  
14,000  
N/A  
20,000  
2,560  
30,000  
3,072  
Logic Modules  
Sequential  
Combinatorial  
Decode  
231  
220  
N/A  
348  
336  
N/A  
624  
608  
N/A  
510  
475  
20  
700  
662  
20  
954  
912  
24  
1,230  
1,184  
24  
1,888  
1,833  
28  
SRAM Modules  
(64x4 or 32x8)  
N/A  
231  
2
N/A  
348  
2
N/A  
624  
2
N/A  
510  
2
8
N/A  
954  
2
10  
1,230  
6
12  
1,888  
6
Dedicated Flip-Flops  
Clocks  
700  
6
User I/O (Maximum)  
JTAG  
83  
104  
No  
140  
No  
126  
No  
152  
Yes  
176  
Yes  
202  
Yes  
250  
Yes  
No  
PL84  
PQ160  
PQ208  
TQ176  
CQ84  
PQ208  
RQ208  
RQ240  
CQ208  
CQ256  
RQ208  
RQ240  
CQ256  
Packages  
PL84  
PL84  
PL84  
PL84 PQ100  
PQ144  
TQ176  
PL84  
PQ160 PQ208  
TQ176  
PQ100  
PQ160  
TQ176  
PQ160  
PQ208  
TQ176  
CQ256  
PQ100  
VQ100  
PG100  
PG132  
PG176 CQ172  
Note: Logic gate capacity does not include SRAM bits as logic.  
February 2001  
1
© 2001 Actel Corporation  
1234567...84

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