Datasheet > 可编程逻辑 > 现场可编程门阵列> A2F060M3E-CSH288YI

A2F060M3E-CSH288YI

更新时间： 2024-11-02 04:12:47

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅现场可编程门阵列可编程逻辑
页数	文件大小	规格书
182页	9722K
描述
Field Programmable Gate Array, 1536 CLBs, 60000 Gates, 80MHz, 1536-Cell, CMOS, PBGA288, 0.50 MM PITCH, HALOGEN FREE, CSP-288

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A2F060M3E-CSH288YI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	0.50 MM PITCH, HALOGEN FREE, CSP-288	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.88
最大时钟频率：	80 MHz	JESD-30 代码：	S-PBGA-B288
长度：	11 mm	可配置逻辑块数量：	1536
等效关口数量：	60000	输入次数：	68
逻辑单元数量：	1536	输出次数：	68
端子数量：	288	组织：	1536 CLBS, 60000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装等效代码：	BGA288,21X21,20	封装形状：	SQUARE
封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH	电源：	1.5,1.8,2.5,3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.05 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
宽度：	11 mm

A2F060M3E-CSH288YI 数据手册

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Revision 7

SmartFusion Customizable System-on-Chip (cSoC)

–

Programmable Embedded FIFO Control Logic

Microcontroller Subsystem (MSS)

•

Secure ISP with 128-Bit AES via JTAG

FlashLock^®to Secure FPGA Contents

Five Clock Conditioning Circuits (CCCs) with up to 2

Integrated Analog PLLs

–

•

Hard 100 MHz 32-Bit ARM^®Cortex™-M3

–

1.25 DMIPS/MHz Throughput from Zero Wait State

Memory

–

Memory Protection Unit (MPU)

Phase Shift, Multiply/Divide, and Delay Capabilities

Frequency: Input 1.5–350 MHz, Output 0.75 to

350 MHz

Single Cycle Multiplication, Hardware Divide

JTAG Debug (4 wires), Serial Wire Debug (SWD, 2

wires), and Single Wire Viewer (SWV) Interfaces

•

Internal Memory

Programmable Analog

–

Embedded Nonvolatile Flash Memory (eNVM), 128

Kbytes to 512 Kbytes

Analog Front-End (AFE)

•

Up to Three 12-Bit SAR ADCs

–

Embedded High-Speed SRAM (eSRAM), 16 Kbytes

to 64 Kbytes, Implemented in 2 Physical Blocks to

–

500 Ksps in 12-Bit Mode

550 Ksps in 10-Bit Mode

600 Ksps in 8-Bit Mode

Enable Simultaneous Access from

Masters

2 Different

•

Multi-Layer AHB Communications Matrix

•

Internal 2.56

Reference

Reference or Optional External

–

Provides up to 16 Gbps of On-Chip Memory

Bandwidth,¹Allowing Multi-Master Schemes

One First-Order ΣΔ DAC (sigma-delta) per ADC

12-Bit 500 Ksps Update Rate

•

10/100 Ethernet MAC with RMII Interface²

Programmable External Memory Controller, Which

Supports:

–

Up to 5 High-Performance Analog Signal Conditioning

Blocks (SCB) per Device, Each Including:

–

Asynchronous Memories

NOR Flash, SRAM, PSRAM

Synchronous SRAMs

–

Two High-Voltage Bipolar Voltage Monitors (with 4

input ranges from ±2.5 V to –11.5/+14 V) with 1%

Accuracy

High Gain Current Monitor, Differential Gain = 50, up

to 14 V Common Mode

•

Two I²C Peripherals

–

Two 16550 Compatible UARTs

Two SPI Peripherals

Two 32-Bit Timers

32-Bit Watchdog Timer

8-Channel DMA Controller to Offload the Cortex-M3

from Data Transactions

Clock Sources

–

Temperature Monitor (Resolution = ¼°C in 12-Bit

Mode; Accurate from –55°C to 150°C)

•

Up to Ten High-Speed Voltage Comparators

(t_pd= 15 ns)

Analog Compute Engine (ACE)

•

Offloads Cortex-M3–Based MSS from Analog

Initialization and Processing of ADC, DAC, and SCBs

Sample Sequence Engine for ADC and DAC Parameter

Set-Up

•

32 KHz to 20 MHz Main Oscillator

Battery-Backed 32 KHz Low Power Oscillator with

Real-Time Counter (RTC)

100 MHz Embedded RC Oscillator; 1% Accurate

Embedded Analog PLL with 4 Output Phases (0, 90,

180, 270)

Post-Processing Engine for Functions such as Low-

Pass Filtering and Linear Transformation

Easily Configured via GUI in Libero^®Integrated Design

(IDE) Software

–

High-Performance FPGA

I/Os and Operating Voltage

•

Based on proven ProASIC^®3 FPGA Fabric

Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,

Flash-Based CMOS Process

•

FPGA I/Os

–

LVDS, PCI, PCI-X, up to 24 mA IOH/IOL

Up to 350 MHz

•

Nonvolatile, Live at Power-Up, Retains Program When

Powered Off

•

MSS I/Os

•

350 MHz System Performance

Embedded SRAMs and FIFOs

–

Schmitt Trigger, up to 6 mA IOH, 8 mA IOL

Up to 180 MHz

–

Variable Aspect Ratio 4,608-Bit SRAM Blocks

x1, x2, x4, x9, and x18 Organizations

True Dual-Port SRAM (excluding x18)

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

External 1.5 V Is Allowed by Bypassing Regulator

(digital VCC = 1.5 V for FPGA and MSS, analog VCC =

3.3 V and 1.5 V)

1 Theoretical maximum

2 A2F200 and larger devices

August 2011

12 3 4 5 6 7...182

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