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A14100AA-1PL208B PDF预览

A14100AA-1PL208B

更新时间: 2022-12-17 00:16:47
品牌 Logo 应用领域
ACTEL /
页数 文件大小 规格书
68页 480K
描述
Accelerator Series FPGAs - ACT 3Family

A14100AA-1PL208B 数据手册

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P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )  
1 7 5 -P in C P G A (T o p Vie w )  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
1
2
3
3
4
4
5
5
6
6
7
7
175-Pin  
CPGA  
8
8
9
9
10  
11  
12  
13  
14  
15  
10  
11  
12  
13  
14  
15  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A1440 Function  
Location  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
C9  
A9  
D5  
D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8,  
M12  
GND  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
R8  
E12  
P13  
F3  
NC  
A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15  
PRA OR I/O  
PRB or I/O  
SDI or I/O  
B8  
R7  
D3  
V
C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13  
CC  
Notes:  
1. Unused I/O pins are designated as outputs by ALS and are driven low.  
2. All unassigned pins are available for use as I/Os.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.  
1 -2 4 0  

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