Datasheet > A14100AA-1PL208B

A14100AA-1PL208B

更新时间： 2022-12-17 00:16:47

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
描述
Accelerator Series FPGAs - ACT 3Family

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A14100AA-1PL208B 数据手册

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

1 0 0 -P in C P G A (T o p Vie w )

10 11

100-Pin

CPGA

10 11

Orientation Pin

A1415 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

C3, C6, C9, E9, F3, F9, J3, J6, J8, J9

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

C10

PRA OR I/O

PRB or I/O

SDI or I/O

B6, B10, E11, F2, F10, G2, K2, K6, K10

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 8

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型号	品牌	描述	获取价格	数据表
A14100AA-1PL208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PL208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PL208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格