Datasheet > A14100AA-1PL208M

A14100AA-1PL208M

更新时间： 2022-12-17 00:16:47

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
描述
Accelerator Series FPGAs - ACT 3Family

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数据手册

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A14100AA-1PL208M 数据手册

Accelerator Series FPGAs

– ACT^™3 Family

F e a t u r e s

• Replaces up to twenty 32 macro-cell CPLDs

• Replaces up to one hundred 20-pin PAL^®Packages

• Up to 1153 Dedicated Flip-Flops

• Up to 10,000 Gate Array Equivalent Gates

(up to 25,000 equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic

Placement and Routing

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• 7.5 ns Clock-to-Output Times

• Fully Tested Prior to Shipment

• Up to 250 MHz On-Chip Performance

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

• More than 500 Macro Functions

• 5.0V and 3.3V Versions

• Optimized for Logic Synthesis Methodologies

• Low-power CMOS Technology

Device

A1415

A1425

A1440

A1460

A14100

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

1,500

3,750

2,500

6,250

4,000

10,000

100

6,000

15,000

150

10,000

25,000

250

100

Logic Modules

S-Module

C-Module

200

104

310

160

150

564

288

276

848

432

416

1,377

697

680

Dedicated Flip-Flops

264

360

100

568

140

768

168

1,153

228

User I/Os (maximum)

Packages (by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

100

—

100

—

133

100, 160

—

175

160

—

100

176

—

207

—

160, 208

—

257

—

208

—

100

—

132

—

176

225

196

313

256

CQFP

—

Performance (maximum, worst-case commercial)

Chip-to-Chip

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

100 MHz

63 MHz

110 MHz

250 MHz

8.5 ns

97 MHz

63 MHz

110 MHz

200 MHz

9.0 ns

93 MHz

63 MHz

105 MHz

200 MHz

9.5 ns

Accumulators (16-bit)

Loadable Counter (16-bit)

Prescaled Loadable Counters (16-bit)

Datapath, Shift Registers

Clock-to-Output (pad-to-pad)

Notes:

1. One flip-flop per S-Module, two flip-flops per I/O-Module.

2. See product plan on page 1-178 for package availability.

3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.

4. Clock-to-Output + Setup

S e p t e m b e r 1 9 9 7

1 -1 7 5

12 3 4 5 6 7...68

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A14100AA-1PQ208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1RQ208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1RQ208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格