Datasheet > A14100AA-1PL208B

A14100AA-1PL208B

更新时间： 2022-12-17 00:16:47

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
描述
Accelerator Series FPGAs - ACT 3Family

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数据手册

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A14100AA-1PL208B 数据手册

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A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

P a c k a g e P i n A s s i g n m e n t s (c o n t in u e d )

3 1 3 -P in B G A (T o p Vie w )

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

A14100

A14V100 Function

Location

CLKA or I/O

CLKB or I/O

DCLK or I/O

GND

J13

G13

A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13

HCLK or I/O

IOCLK or I/O

IOPCL or I/O

MODE

T14

B24

AD24

A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25,

D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7,

N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24

PRA OR I/O

PRB or I/O

SDI or I/O

H12

AD12

AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24

Notes:

1. Unused I/O pins are designated as outputs by ALS and are driven low.

2. All unassigned pins are available for use as I/Os.

3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.

1 -2 3 7

1...60 61 626364 65 66...68

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与A14100AA-1PL208B相关器件

型号	品牌	描述	获取价格	数据表
A14100AA-1PL208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PL208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PL208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格