Datasheet > A14100AA-1CQ208C

A14100AA-1CQ208C

更新时间： 2022-12-17 00:16:47

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
描述
Accelerator Series FPGAs - ACT 3Family

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™

A c c e l e r a t o r S e r i e s F P G A s – A C T

3 F a m i l y

MUX

DATAOUT

MUX

CLR/PRE

ODE

MUX

DATAIN

CLR/PRE

IOPCL

IOCLK

Figure 4 • Functional Diagram for I/O Module

I/O Pad Drivers

buffer (IOPCL). Their function is determined by the I/O

macros selected.

All pad drivers are capable of being tristate. Each buffer

connects to an associated I/O module with four signals: OE

(Output Enable), IE (Input Enable), DataOut, and DataIn.

Certain special signals used only during programming and

test also connect to the pad drivers: OUTEN (global output

enable), INEN (global input enable), and SLEW (individual

slew selection). See Figure 5.

C lo c k N e t w o r k s

The ACT 3 architecture contains four clock networks: two

high-performance dedicated clock networks and two general

purpose routed networks. The high-performance networks

function up to 200 MHz, while the general purpose routed

networks function up to 150 MHz.

Special I/Os

Dedicated Clocks

The special I/Os are of two types: temporary and permanent.

Temporary special I/Os are used during programming and

testing. They function as normal I/Os when the MODE pin is

inactive. Permanent special I/Os are user programmed as

either normal I/Os or special I/Os. Their function does not

change once the device has been programmed. The

permanent special I/Os consist of the array clock input

buffers (CLKA and CLKB), the hard-wired array clock input

buffer (HCLK), the hard-wired I/O clock input buffer

(IOCLK), and the hard-wired I/O register preset/clear input

Dedicated clock networks support high performance by

providing sub-nanosecond skew and guaranteed

performance. Dedicated clock networks contain no

programming elements in the path from the I/O Pad Driver to

the input of S-modules or I/O modules. There are two

dedicated clock networks: one for the array registers (HCLK),

and one for the I/O registers (IOCLK). The clock networks

are accessed by special I/Os.

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与A14100AA-1CQ208C相关器件

型号	品牌	描述	获取价格	数据表
A14100AA-1CQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1CQ208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格