H e r m e t i c D e v i c e R e s o u r c e s
User I/Os
CPGA
CQFP
Device
Series
Logic
Modules
Gates
100-pin 133-pin 175-pin 207-pin 257-pin 132-pin 196-pin 256-pin
A1415
A1425
A1440
A1460
A14100
200
310
1500
2500
4000
6000
10000
80
—
—
—
—
—
100
—
—
—
—
—
—
—
—
100
—
—
—
—
—
564
140
—
—
—
—
—
848
—
168
—
—
—
168
—
—
1377
—
—
228
—
228
P i n D e s c r i p t i o n
function as I/Os. To provide Actionprobe capability, the
MODE pin should be terminated to GND through a 10K
resistor so that the MODE pin can be pulled high when
required.
C LK A
C lo c k A (In p u t )
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
N C
N o C o n n e c t io n
This pin is not connected to circuitry within the device.
C LK B
C lo c k B (In p u t )
P R A
P r o b e A (O u t p u t )
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
G N D
G r o u n d
LOW supply voltage.
H C LK
De d ic a t e d (H a r d -w ir e d )
Ar r a y C lo c k (In p u t )
Clock input for sequential modules. This input is directly
wired to each S-Module and offers clock speeds independent
of the number of S-Modules being driven. This pin can also be
used as an I/O.
P R B
P r o b e B (O u t p u t )
I/O
In p u t /O u t p u t (In p u t , O u t p u t )
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are tristated by the Designer Series software.
IO C LK
De d ic a t e d (H a r d -w ir e d )
I/O C lo c k (In p u t )
Clock input for I/O modules. This input is directly wired to
each I/O module and offers clock speeds independent of the
number of I/O modules being driven. This pin can also be
used as an I/O.
S DI
S e r ia l Da t a In p u t (In p u t )
IO P C L
De d ic a t e d (H a r d -w ir e d )
I/O P r e s e t /C le a r (In p u t )
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
Input for I/O preset or clear. This global input is directly
wired to the preset and clear inputs of all I/O registers. This
pin functions as an I/O when no I/O preset or clear macros
are used.
DC LK
Dia g n o s t ic C lo c k (In p u t )
Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
MO DE
Mo d e (In p u t )
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
V
5 V S u p p ly Vo lt a g e
C C
HIGH supply voltage.
1 -1 8 0
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