Datasheet > A14100AA-1CQ208C

A14100AA-1CQ208C

更新时间： 2022-12-17 00:16:47

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
68页	480K
描述
Accelerator Series FPGAs - ACT 3Family

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A14100AA-1CQ208C 数据手册

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The S-module contains a full implementation of the C-module

plus a clearable sequential element that can either

implement a latch or flip-flop function. The S-module can

therefore implement any function implemented by the

C-module. This allows complex combinatorial-sequential

functions to be implemented with no delay penalty. The

Designer Series Development System will automatically

combine any C-module macro driving an S-module macro into

the S-module, thereby freeing up a logic module and

eliminating a module delay.

D00

D01

D10

OUT

D11

The clear input CLR is accessible from the routing channel.

In addition, the clock input may be connected to one of three

clock networks: CLKA, CLKB, or HCLK. The C-module and

S-module functional descriptions are shown in Figures 2

and 3. The clock selection is determined by a multiplexor

select at the clock input to the S-module.

A1 B1

A0 B0

I/O s

Figure 2 • C-Module Diagram

I/O Modules

preset/clear network (IOPCL). Either preset or clear can be

selected individually on an I/O module by I/O module basis.

I/O modules provide an interface between the array and the

I/O Pad Drivers. I/O modules are located in the array and

access the routing channels in a similar fashion to logic

modules. The I/O module schematic is shown in Figure 4. The

signals DataIn and DataOut connect to the I/O pad driver.

Each I/O module contains two D-type flip-flops. Each flip-flop

is connected to the dedicated I/O clock (IOCLK). Each

flip-flop can be bypassed by nonsequential I/Os. In addition,

each flip-flop contains a data enable input that can be

accessed from the routing channels (ODE and IDE). The

asynchronous preset/clear input is driven by the dedicated

The I/O module output Y is used to bring Pad signals into the

array or to feed the output register back into the array. This

allows the output register to be used in high-speed state

machine applications. Side I/O modules have a dedicated

output segment for Y extending into the routing channels

above and below (similar to logic modules). Top/Bottom I/O

modules have no dedicated output segment. Signals coming

into the chip from the top or bottom are routed using F-fuses

and LVTs (F-fuses and LVTs are explained in detail in the

routing section).

D00

D01

OUT

D10

D11

CLK

CLR

A1 B1

A0 B0

Figure 3 • S-Module Diagram

1 -1 8 2

1...5 6 789 10 11...68

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与A14100AA-1CQ208C相关器件

型号	品牌	描述	获取价格	数据表
A14100AA-1CQ208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1CQ208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208B	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208C	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208I	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格
A14100AA-1PG208M	ACTEL	Accelerator Series FPGAs - ACT 3Family	获取价格