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A1010B-3PQ100C

更新时间： 2024-11-11 21:11:59
品牌 Logo 应用领域
ACTEL 栅
页数 文件大小 规格书
24页 163K
描述
Field Programmable Gate Array, 295 CLBs, 1200 Gates, 70MHz, 295-Cell, CMOS, PQFP100, PLASTIC, MO-108, QFP-100

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A1010B-3PQ100C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：PLASTIC, MO-108, QFP-100Reach Compliance Code：unknown
风险等级：5.87其他特性：MAX 57 I/OS
最大时钟频率：70 MHzCLB-Max的组合延迟：2.9 ns
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm湿度敏感等级：3
可配置逻辑块数量：295等效关口数量：1200
输入次数：57逻辑单元数量：295
输出次数：57端子数量：100
最高工作温度：70 °C最低工作温度：
组织：295 CLBS, 1200 GATES封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.7X.9
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：225电源：5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：3.4 mm子类别：Field Programmable Gate Arrays
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

A1010B-3PQ100C 数据手册

 浏览型号A1010B-3PQ100C的Datasheet PDF文件第2页浏览型号A1010B-3PQ100C的Datasheet PDF文件第3页浏览型号A1010B-3PQ100C的Datasheet PDF文件第4页浏览型号A1010B-3PQ100C的Datasheet PDF文件第5页浏览型号A1010B-3PQ100C的Datasheet PDF文件第6页浏览型号A1010B-3PQ100C的Datasheet PDF文件第7页 
ACT™ 1 Series FPGAs  
F e a t u r e s  
A security fuse may be programmed to disable all further  
programming and to protect the design from being copied or  
reverse engineered.  
• 5V and 3.3V Families fully compatible with JEDEC  
specifications  
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)  
• Replaces up to 50 TTL Packages  
• Replaces up to twenty 20-Pin PAL® Packages  
P r o d u c t F a m i l y P r o f i l e  
A1010B  
A1020B  
Device  
A10V10B A10V20B  
• Design Library with over 250 Macro Functions  
Capacity  
Gate Array Equivalent Gates  
PLD Equivalent Gates  
TTL Equivalent Packages  
20-Pin PAL Equivalent Packages  
1,200  
3,000  
30  
2,000  
6,000  
50  
• Gate Array Architecture Allows Completely Automatic  
Place and Route  
12  
20  
• Up to 547 Programmable Logic Modules  
• Up to 273 Flip-Flops  
Logic Modules  
295  
147  
547  
273  
Flip-Flops (maximum)  
• Data Rates to 75 MHz  
Routing Resources  
• Two In-Circuit Diagnostic Probe Pins Support Speed  
Analysis to 25 MHz  
Horizontal Tracks/Channel  
Vertical Tracks/Column  
PLICE Antifuse Elements  
22  
13  
22  
13  
• Built-In High Speed Clock Distribution Network  
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)  
• Nonvolatile, User Programmable  
112,000  
186,000  
User I/Os (maximum)  
Packages:  
57  
69  
44 PLCC 44 PLCC  
68 PLCC 68 PLCC  
84 PLCC  
• Fabricated in 1.0 micron CMOS technology  
100 PQFP 100 PQFP  
80 VQFP 80 VQFP  
84 CPGA 84 CPGA  
84 CQFP  
D e s c r i p t i o n  
The ACT™ 1 Series of field programmable gate arrays  
(FPGAs) offers a variety of package, speed, and application  
combinations. Devices are implemented in silicon gate,  
1-micron two-level metal CMOS, and they employ Actel’s  
PLICE® antifuse technology. The unique architecture offers  
gate array flexibility, high performance, and instant  
turnaround through user programming. Device utilization is  
typically 95 to 100 percent of available logic modules.  
Performance  
5 V Data Rate (maximum)  
3.3 V Data Rate (maximum)  
75 MHz  
55 MHz  
75 MHz  
55 MHz  
Note: See Product Plan on page 1-286 for package availability.  
T h e D e s i g n e r a n d D e s i g n e r  
A d v a n t a g e ™ S y s t e m s  
ACT 1 devices also provide system designers with unique  
on-chip diagnostic probe capabilities, allowing convenient  
testing and debugging. Additional features include an on-chip  
clock driver with a hardwired distribution network. The  
network provides efficient clock distribution with minimum  
skew.  
The ACT 1 device family is supported by Actel’s Designer and  
Designer Advantage Systems, allowing logic design  
implementation with minimum effort. The systems offer  
Microsoft® Windows™ and X Windows™ graphical user  
interfaces and integrate with the resident CAE system to  
provide a complete gate array design environment: schematic  
capture, simulation, fully automatic place and route, timing  
verification, and device programming. The systems also  
include the ACTmap™ VHDL optimization and synthesis tool  
and the ACTgen™ Macro Builder, a powerful macro function  
generator for counters, adders, and other structural blocks.  
The user-definable I/Os are capable of driving at both TTL  
and CMOS drive levels. Available packages include plastic  
and ceramic J-leaded chip carriers, ceramic and plastic quad  
flatpacks, and ceramic pin grid array.  
A p r i l 1 9 9 6  
1 -2 8 3  
© 1996 Actel Corporation  
1234567...24

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