Datasheet > 9ZXL0852E

9ZXL0852E

更新时间： 2022-02-26 10:34:30

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	274K
描述
8-Output DB800ZL Derivative PCIe Gen1â4 and UPI

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9ZXL0852E 数据手册

9ZXL0832E / 9ZXL0852E Datasheet

Electrical Characteristics–Input/Supply/Common Output Parameters

T_AMB= over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions

Symbol

VDDx

VDDIO

Parameter

Supply Voltage

Output Supply Voltage

Ambient Operating

Temperature

Conditions

Supply voltage for core and analog

Supply voltage for DIF outputs, if present

Minimum Typical Maximum

Units Notes

3.135

0.9975

3.3

1.05

3.465

T_AMB

Industrial range (T_IND

)

-40

°C

V_IH

V_IL

V_IH

V_IL

I_IN

Input High Voltage

Input Low Voltage

Input High Voltage

Input Mid Voltage

Input Low Voltage

Single-ended inputs, except SMBus, tri-level inputs

V_DD+ 0.3

0.8

Single-ended inputs, except SMBus, tri-level inputs GND - 0.3

Tri-level inputs

2.2

1.2

V_DD+ 0.3

1.8

VDD/2

GND - 0.3

-5

0.8

Single-ended inputs, V_IN= GND, V_IN= V_DD

Single-ended inputs

μA

Input Current

V_IN= 0 V; inputs with internal pull-up resistors

I_INP

-50

μA

V_IN= V_DD; inputs with internal pull-down resistors

V_DD= 3.3 V, Bypass Mode

F_ibyp

F_ipll

400

102.5

135

MHz

Input Frequency

Pin Inductance

Capacitance

V_DD= 3.3 V, 100MHz PLL Mode

98.5

132

100.00

133.33

F_ipll

V_DD= 3.3 V, 133.33MHz PLL Mode

L_pin

C_IN

Logic inputs, except DIF_IN

DIF_IN differential clock inputs

1.5

C_{INDIF_IN}

C_OUT

2.7

1,4

Output pin capacitance

From V_DDpower-up and after input clock stabilization

T_STAB

Clk Stabilization

1.0

1.8

1,2

or de-assertion of PD# to 1st clock

Allowable frequency for PCIe applications

(Triangular modulation)

Input SS Modulation

Frequency PCIe

f_MODINPCIe

t_LATOE#

t_DRVPD

kHz

clocks

μs

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

OE# Latency

Tdrive_PD#

1,2,3

1,3

300

PD# de-assertion

t_F

Tfall

Fall time of control inputs

t_R

Trise

Rise time of control inputs

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are > 200mV.

⁴DIF_IN input.

August 14, 2018

1...3 4 567 8 9...18

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