Datasheet > 9ZXL0651EKILFT

9ZXL0651EKILFT

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	303K
描述
6-Output DB800ZL Derivative for PCIe Gen1â4 and UPI

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9ZXL0651EKILFT 数据手册

9ZXL0631E / 9ZXL0651E Datasheet

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

VDDA

Power

Power supply for PLL core.

Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kΩ

pull-up resistor. See PLL Operating Mode table for details.

^HIBW_BYPM_LOBW#

^CKPWRGD_PD#

Latched In

Input

Input notifies device to sample latched inputs and start up on first high assertion. Low

enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin

has internal 120kΩ pull-up resistor.

GND

Ground pin.

Power supply for differential input clock (receiver). This V should be treated as an

analog power rail and filtered appropriately. Nominally 3.3V.

VDDR

Power

DIF_IN

DIF_IN#

SMBDAT

SMBCLK

Input

I/O

HCSL true input.

HCSL complementary input.

Data pin of SMBUS circuitry.

Input

Clock pin of SMBUS circuitry.

Complementary half of differential feedback output. This pin should NOT be connected

to anything outside the chip. It exists to provide delay path matching to get 0

propagation delay.

FBOUT_NC#

Output

True half of differential feedback output. This pin should NOT be connected to anything

outside the chip. It exists to provide delay path matching to get 0 propagation delay.

FBOUT_NC

VDD

Output

Power

Input

Power supply, nominally 3.3V.

Active low input for enabling output 0. This pin has an internal 120kΩ pull-down.

vOE0#

1 = disable outputs, 0 = enable outputs.

DIF0

DIF0#

VDD

Output

Power

Output

Differential true clock output.

Differential complementary clock output.

Power supply, nominally 3.3V.

DIF1

Differential true clock output.

DIF1#

Differential complementary clock output.

Active low input for enabling output 1. This pin has an internal 120kΩ pull-down.

vOE1#

Input

1 = disable outputs, 0 = enable outputs.

VDD

Power

Power supply, nominally 3.3V.

Active low input for enabling output 2. This pin has an internal 120kΩ pull-down.

vOE2#

Input

1 = disable outputs, 0 = enable outputs.

DIF2

DIF2#

VDD

Output

Power

Output

Differential true clock output.

Differential complementary clock output.

Power supply, nominally 3.3V.

DIF3

Differential true clock output.

DIF3#

Differential complementary clock output.

August 14, 2018

1 2 345 6 7...20

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