Datasheet > 9ZXL0451E

9ZXL0451E

更新时间： 2023-12-20 18:44:10

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
34页	1350K
描述
4-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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9ZXL0451E 数据手册

9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet

Table 1. Pin Descriptions (Cont.)

9ZXL12x1 9ZXL08x1 9ZXL06x1 9ZXL04x1

Name

Type

Description

Pin No.

Active low input for enabling output 11. This pin has an internal

pull-down.

vOE11#

Input

1 = disable output, 0 = enable output.

Active low input for enabling output 2. This pin has an internal

pull-down.

vOE2#

vOE3#

vOE4#

vOE5#

vOE6#

vOE7#

vOE8#

vOE9#

Input

n/a

1 = disable output, 0 = enable output.

Active low input for enabling output 3. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 4. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 5. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 6. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 7. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 8. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

Active low input for enabling output 9. This pin has an internal

pull-down.

1 = disable output, 0 = enable output.

SMBus address bit. This is a tri-level input that works in

conjunction with other SADR pins, if present, to decode SMBus

Addresses. It has an internal pull down resistor. See the

SMBus Addresses table.

vSADR0_tri

vSADR1_tri

Input

SMBus address bit. This is a tri-level input that works in

conjunction with other SADR pins, if present, to decode SMBus

Addresses. It has an internal pull down resistor. See the

SMBus Addresses table.

December 19, 2022

1...6 7 8910 11 12...34

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