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9ZXL0451E PDF预览

9ZXL0451E

更新时间: 2023-12-20 18:44:10
品牌 Logo 应用领域
瑞萨 - RENESAS PC
页数 文件大小 规格书
34页 1350K
描述
4-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

9ZXL0451E 数据手册

 浏览型号9ZXL0451E的Datasheet PDF文件第6页浏览型号9ZXL0451E的Datasheet PDF文件第7页浏览型号9ZXL0451E的Datasheet PDF文件第8页浏览型号9ZXL0451E的Datasheet PDF文件第10页浏览型号9ZXL0451E的Datasheet PDF文件第11页浏览型号9ZXL0451E的Datasheet PDF文件第12页 
9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E Datasheet  
Table 1. Pin Descriptions (Cont.)  
9ZXL12x1 9ZXL08x1 9ZXL06x1 9ZXL04x1  
Name  
Type  
Description  
Pin No.  
Pin No.  
Pin No.  
Pin No.  
Active low input for enabling output 11. This pin has an internal  
pull-down.  
vOE11#  
Input  
62  
-
-
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 2. This pin has an internal  
pull-down.  
vOE2#  
vOE3#  
vOE4#  
vOE5#  
vOE6#  
vOE7#  
vOE8#  
vOE9#  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
28  
29  
36  
37  
44  
45  
52  
53  
23  
24  
30  
31  
37  
41  
n/a  
-
22  
28  
32  
38  
-
24  
1 = disable output, 0 = enable output.  
Active low input for enabling output 3. This pin has an internal  
pull-down.  
26  
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 4. This pin has an internal  
pull-down.  
1 = disable output, 0 = enable output.  
Active low input for enabling output 5. This pin has an internal  
pull-down.  
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 6. This pin has an internal  
pull-down.  
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 7. This pin has an internal  
pull-down.  
-
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 8. This pin has an internal  
pull-down.  
-
-
1 = disable output, 0 = enable output.  
Active low input for enabling output 9. This pin has an internal  
pull-down.  
-
-
1 = disable output, 0 = enable output.  
SMBus address bit. This is a tri-level input that works in  
conjunction with other SADR pins, if present, to decode SMBus  
Addresses. It has an internal pull down resistor. See the  
SMBus Addresses table.  
vSADR0_tri  
vSADR1_tri  
Input  
Input  
11  
14  
-
-
-
-
5
-
SMBus address bit. This is a tri-level input that works in  
conjunction with other SADR pins, if present, to decode SMBus  
Addresses. It has an internal pull down resistor. See the  
SMBus Addresses table.  
©2018-2022 Renesas Electronics Corporation  
9
December 19, 2022  

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