Datasheet > 9FGU0241

9FGU0241

更新时间： 2023-12-20 18:46:06

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
16页	392K
描述
2-output 1.5 V PCIe Gen1-2-3 Clock Generator with Zo=100 ohms

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9FGU0241 数据手册

9FGU0241 DATASHEET

General SMBus Serial Interface Information

How to Write

How to Read

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

• IDT clock sends Byte 0 through Byte X (if X was

written to Byte 8)

(H)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Index Block Read Operation

Controller (Host)

IDT (Slave/Receiver)

Controller (Host)

starT bit

IDT (Slave/Receiver)

starT bit

Slave Address

WRite

ACK

Beginning Byte = N

Data Byte Count = X

Beginning Byte N

Beginning Byte = N

Repeat starT

Slave Address

ReaD

ACK

Data Byte Count=X

Beginning Byte N

ACK

Byte N + X - 1

ACK

stoP bit

Note: Read/Write address is determined by SADR latch.

Byte N + X - 1

Not acknowledge

stoP bit

OCTOBER 18, 2016

2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

1...6 7 8910 11 12...16

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