9FGU0241 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.2
0.8
2.4
1.7
9
3.6
2.5
20
1,2,3
1,2,3
1,2,4
Slew rate
Trf
Slew rate matching
Voltage High
Trf
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
VLOW
600
750
26
850
7
7
mV
Voltage Low
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
763
22
1448
390
11
1150
7
7
mV
-300
300
250
Scope averaging off
Scope averaging off
Scope averaging off
mV
mV
mV
1,2,7
1,5,7
1,6,7
Vcross_abs
550
140
Crossing Voltage (var)
-Vcross
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus amplitude settings.
Electrical Characteristics–DIF Output Phase Jitter Parameter
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
IND.
LIMIT
86
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
MIN
TYP
27.7
1.0
MAX
40
UNITS Notes
ps (p-p) 1,2,3,5
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
ps
1.3
3
3.1
1
1,2,3,5
(rms)
tjphPCIeG2
PCIe Gen 2 High Band
ps
2.2
0.6
1.9
0.4
1,2,3,5
(rms)
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
Phase Jitter, PLL Mode
ps
tjphPCIeG3
1,2,3,5
(rms)
tjphPCIeG3SRn
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
ps
0.6
0.7
0.4
1,2,3,5
(rms)
S
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Calculated from Intel-supplied Clock Jitter Tool
5 Applies to all differential outputs
OCTOBER 18, 2016
7
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
