9FGP204
Frequency Timing Generator for Peripherals
General SMBus serial interface information for the 9FGP204
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0(H)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D0(H)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1(H)
• ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address *D0(H)
Slave Address *D0(H)
WR
WRite
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address *D1(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
* The SMBus address depends on the latched value of pin 22.
Please see SMBus Address Selection table on page 1.
IDT® Frequency Timing Generator for Peripherals
1604B—08/29/11
12