9FGP204
Frequency Timing Generator for Peripherals
Revision History
Rev. Issue Date
Who
RDW
RDW
Description
Initial Release
Page #
0.1
0.2
6/8/2009
11/9/2009
-
Updated SMBus Byte 4 bits 0, 1 to reserved
1. Updated Series Termination values
2. Added separate Table for RGMII output.
1. Updated Series Termination values and highlighted values are for Zo
= 50 ohms.
0.3
1/29/2010
RDW
2. Raised Idd MAX to 225mA from 200 mA
3. Adding Rise/Fall Matching spec to CPU and DOT96SS Electrical
Tables.
4, 7, 8,
4. Removed All CPU frequencies except 100 from CPU Electrical
Table.
9, 10, 11
5. Updated Min/Max clock periods to reflect new 50 ps cycle to cycle
jitter limit on CPU output.
A
B
4/7/2010
8/29/2011
RDW
RDW
4. Updated electrical tables with typical values from char report.
1. Removed OE pins for RMII from the block diagram.
3
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©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks
a
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
18