Datasheet > 9FGL0251BKILFT

9FGL0251BKILFT

更新时间： 2022-02-26 10:49:50

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	370K
描述
2-output 3.3V PCIe Clock Generator

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

9FGL0251BKILFT 数据手册

9FGL02 DATASHEET

Electrical Characteristics–Current Consumption

TA = T_AMB;Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

I_DDAOP

I_DDOP

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

VDDA, All outputs active @100MHz

All VDD, except VDDA, All outputs active

@100MHz

Operating Supply Current

Wake-on-LAN Current

(Power down state and

Byte 3, bit 5 = '1')

Powerdown Current

(Power down state and

Byte 3, bit 5 = '0')

I_DDAPD

I_DDPD

I_DDAPD

I_DDPD

VDDA, DIF outputs off, REF output running

All VDD, except VDDA,

0.7

8.8

0.7

4.7

1.5

DIF outputs off, REF output running

VDDA, all outputs off

1.5

All VDD, except VDDA, all outputs off

¹This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)

Electrical Characteristics– REF

TA = T_AMB;Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS Notes

Long Accuracy

Clock period

ppm

T_period

see Tperiod min-max values

REF output

ppm

1,2

High output Voltage

Low output Voltage

V_HIGH

I_OH= -2mA

0.8xV_DDREF

V_LOW

t_rf1

I_OL= 2mA

Byte 3 = 1F, V_OH= 0.8*VDD, V_OL= 0.2*VDD

Byte 3 = 5F, VOH = 0.8*VDD, VOL = 0.2*VDD

Byte 3 = 9F, VOH = 0.8*VDD, VOL = 0.2*VDD

Byte 3 = DF, VOH = 0.8*VDD, VOL = 0.2*VDD

V_T= VDD/2 V

0.2xV_DDREF

1.2

0.5

1.0

1.5

2.0

0.9

1.5

2.2

2.9

50.2

V/ns

t_rf1

2.0

1,3

Rise/Fall Slew Rate

t_rf1

2.6

t_rf1

3.2

Duty Cycle

d_t1X

1,4

1,5

1,4

Duty Cycle Distortion

Jitter, cycle to cycle

d_tcd

V_T= VDD/2 V

-1

t_jcyc-cyc

t_jdBc1k

t_jdBc10k

t_jphREF

V_T= VDD/2 V

150

-135

-140

0.3

1kHz offset

-145

-150

0.13

dBc

Noise floor

10kHz offset to Nyquist

12kHz to 5MHz, DIF SSC Off

ps (rms) 1,4

Jitter, phase

t_jphREF

12kHz to 5MHz, DIF SSC On

1.5

¹Guaranteed by design and characterization, not 100% tested in production.

²All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz

³Default SMBus Value

⁴When driven by a crystal.

⁵When driven by an external oscillator via the X1 pin, X2 should be floating.

OCTOBER 18, 2016

2-OUTPUT 3.3V PCIE CLOCK GENERATOR

1...6 7 8910 11 12...19

下载PDF

与9FGL0251BKILFT相关器件

型号	品牌	描述	获取价格	数据表
9FGL04	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL04	RENESAS	4-Output 3.3V PCIe Gen1–5 Clock Generator	获取价格
9FGL04_16	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL0441BKILF	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL0441BKILFT	IDT	4-output 3.3V PCIe Clock Generator	获取价格
9FGL0451BKILF	IDT	4-output 3.3V PCIe Clock Generator	获取价格