Datasheet > 9FGL0251BKILFT

9FGL0251BKILFT

更新时间： 2022-02-26 10:49:50

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
19页	370K
描述
2-output 3.3V PCIe Clock Generator

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数据手册

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9FGL0251BKILFT 数据手册

9FGL02 DATASHEET

SMBus Table: Pull-up Pull-down Control

Byte 16

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Type

Default

Reserved

CKPWRGD_PD_pu/pd[1]

CKPWRGD_PD_pu/pd[0]

CKPWRGD_PD Pull-up(PuP)/ RW

00=None

01=Pdwn

10=Pup

11 = Pup+Pdwn

Pull-down(Pdwn) control

Byte 17 is Reserved

SMBus Table: Polarity Control

Byte 18

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Control Function

Reserved

Sets OE1 polarity

Reserved

Type

Default

OE1_polarity

OE0_polarity

RW Enabled when Low Enabled when High

Sets OE0 polarity

Reserved

SMBus Table: Polarity Control

Byte 19

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Name

Control Function

Reserved

Type

Default

Reserved

Determines

CKPWRGD_PD polarity

Power Down when Power Down when

Low High

CKPWRGD_PD

Bit 0

2-OUTPUT 3.3V PCIE CLOCK GENERATOR

OCTOBER 18, 2016

1...11 12 131415 16 17...19

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