Datasheet > 9FG104YFT

9FG104YFT

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
17页	238K
描述
Processor Specific Clock Generator, 400MHz, PDSO28, 0.209 INCH, MO-150N, SSOP-28

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9FG104YFT 数据手册

ICS9FG104

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

SMBus Table: PLL Frequency Control Register

Byte 11

Pin #

Name

Control Function

Type

PWD

PLL N Div7

PLL N Div6

PLL N Div5

PLL N Div4

PLL N Div3

PLL N Div2

PLL N Div1

PLL N Div0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The decimal representation of M

and N Divider in Byte 11 and 12 will

configure the PLL VCO frequency.

Default at power up = latch-in or

Byte 0 Rom table. VCO Frequency

= 14.318 x [NDiv(9:0)+8] /

N Divider Programming

Byte11 bit(7:0) and Byte10

bit(7:6)

[MDiv(5:0)+2]

SMBus Table: PLL Spread Spectrum Control Register

Byte 12

Pin #

Name

Control Function

Type

PWD

PLL SSP7

PLL SSP6

PLL SSP5

PLL SSP4

PLL SSP3

PLL SSP2

PLL SSP1

PLL SSP0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

These Spread Spectrum bits in

Byte 13 and 14 will program the

spread pecentage of PLL

Spread Spectrum

Programming bit(7:0)

SMBus Table: PLL Spread Spectrum Control Register

Byte 13

Pin #

Name

Control Function

Type

PWD

Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL SSP14

PLL SSP13

PLL SSP12

PLL SSP11

PLL SSP10

PLL SSP9

PLL SSP8

These Spread Spectrum bits in

Byte 13 and 14 will program the

spread pecentage of PLL

Spread Spectrum

Programming bit(14:8)

SMBus Table: Reserved Test Register

Byte 14

Pin #

Name

Control Function

Type

PWD

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved Test Register. Do not write to this register, erratic device operation may occur.

IDT^TM/ICS^TMFrequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

0839O—12/03/08

1...5 6 789 10 11...17

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